Semiconductor device and method of forming the same

ABSTRACT

A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device and amethod of forming the same. More specifically, the present inventionrelates to a semiconductor device including a DRAM capacitor with abottom electrode having an improved adhesiveness with an adjacentinsulating film.

Priority is claimed on Japanese Patent Application No. 2006-211168,filed Aug. 2, 2006, the content of which is incorporated herein byreference.

2. Description of the Related Art

All patents, patent applications, patent publications, scientificarticles, and the like, which will hereinafter be cited or identified inthe present application, will hereby be incorporated by reference intheir entirety in order to describe more fully the state of the art towhich the present invention pertains.

A memory cell such as a DRAM (Dynamic Random Access Memory) includes aswitching transistor and a capacitor. The advanced microprocessingtechnique has realized shrinkage of the memory cell, which decreases thecharge storage capacity of a memory cell. In order to solve thedisadvantages of the decrease of the charge storage capacity, a COB(capacitor over bit-line) structure and an STC (stacked trenchcapacitor) structure have been used in constituting the memory cell. Inthe memory cell, a capacitor is disposed over a bit-line so as to allowthe increases in the projected area and the height of the capacitor,thereby allowing the increase in the area of a capacitor electrode orelectrodes.

Japanese Unexamined Patent Application, First Publication, No.2004-221467 discloses a conventional memory cell structure that isconstituted by the COB and the STC. The capacitor of the memory cell hasa cylindrically shaped bottom electrode which is realized by a rutheniumfilm. The ruthenium film is adjacent to an inter-layer insulator ofsilicon oxide. It is necessary to ensure the adhesiveness between theruthenium film and the silicon oxide film as the inter-layer insulator.In order to ensure the adhesiveness between the ruthenium film and thesilicon oxide film, an adhesive layer is interposed between them. Theadhesive layer can be formed by oxidizing a titanium nitride film. Theadhesive layer is effective to present that during the process forforming a capacitor the ruthenium film as the bottom electrode from ispeeled or removed from the silicon oxide film as the inter-layerinsulator. The adhesive layer provides the adhesiveness between thebottom electrode and the inter-layer insulator, thereby preventing theabove-described problems during the process for forming a capacitor.

In recent years, further shrinkage and high density integration of amemory device such as a DRAM has caused further structural complicationof a capacitor and further increase in the aspect ratio thereof. Theprocess for forming the bottom electrode includes the process forforming an extremely small contact hole with high aspect ratio in asilicon oxide film. In the process, a silicon nitride film is often usedas an etching stopper. The present inventors investigated the problemabout the adhesiveness between the silicon nitride film as the etchingstopper and the bottom electrode film. The adhesive layer of titaniumnitride provides the adhesiveness between the silicon oxide film and thebottom electrode. However, the adhesive layer of titanium nitride doesnot ensure the adhesiveness between the silicon nitride film and thebottom electrode. The process for forming the capacitor includes a heattreatment which may cause the peeling between the silicon nitride filmand the bottom electrode, thereby deforming the bottom electrode. Thedeformed bottom electrode may cause increased leakage of current of thecapacitor. The process for forming the capacitor also includes a wetetching process using an etchant. The peeling between the siliconnitride film and the bottom electrode by the heat treatment may causethe etchant to be drawn into the interface between the silicon nitridefilm and the bottom electrode, thereby causing the bottom electrode tobe inclined or removed.

In view of the above, it will be apparent to those skilled in the artfrom this disclosure that there exists a need for an improvedsemiconductor device and a method of forming the same. This inventionaddresses this need in the art as well as other needs, which will becomeapparent to those skilled in the art from this disclosure.

SUMMARY OF THE INVENTION

Accordingly, it is a primary object of the present invention to providea semiconductor device including a capacitor.

It is another object of the present invention to provide a semiconductordevice including a capacitor with a bottom electrode with an increasedadhesiveness to an adjacent insulating film.

It is a further object of the present invention to provide asemiconductor device including a capacitor with a reduced leakage ofcurrent.

It is a still further object of the present invention to provide asemiconductor device including a capacitor with a bottom electrode whichis free from being inclined or removed in the process of wet etching.

It is yet a further object of the present invention to provide asemiconductor device including a capacitor with improved reliability.

It is an additional object of the present invention to provide a methodof forming a semiconductor device including a capacitor.

It is another object of the present invention to provide a method offorming a semiconductor device including a capacitor with a bottomelectrode with an increased adhesiveness to an adjacent insulating film.

It is still another object of the present invention to provide a methodof forming a semiconductor device including a capacitor with a reducedleakage of current.

It is yet another object of the present invention to provide a method offorming a semiconductor device including a capacitor with a bottomelectrode which is free from being inclined or removed in the process ofwet etching.

It is an additional object of the present invention to provide a methodof forming a semiconductor device including a capacitor with improvedreliability.

It is a further additional object of the present invention to provide amethod of forming a semiconductor device including a capacitor at highyield.

In accordance with a first aspect of the present invention, asemiconductor device may include, but is not limited to, a firstinsulating layer, a capacitor, an adhesive layer, and an intermediatelayer. The first insulating layer may include a first insulating film.The first insulating layered structure has a first hole. The capacitoris disposed in the first hole. The capacitor may include bottom and topelectrodes and a capacitive insulating film. The capacitive insulatingfilm is sandwiched between the bottom and top electrodes. The adhesivelayer contacts with the bottom electrode. The adhesive layer hasadhesiveness to the bottom electrode. The intermediate layer isinterposed between the adhesive layer and the first insulating film. Theintermediate layer contacts with the adhesive layer and with the firstinsulating film. The intermediate layer has adhesiveness to the adhesivelayer and to the first insulating film.

In accordance with a second aspect of the present invention, asemiconductor device may include, but is not limited to, a firstinsulating layer, a capacitor, and an adhesive layer. The firstinsulating layer may include a first insulating film, the firstinsulating layered structure having a first hole. The capacitor may bedisposed in the first hole. The capacitor may include, but is notlimited to, bottom and top electrodes and a capacitive insulating filmthat is sandwiched between the bottom and top electrodes. The adhesivelayer may be interposed between the bottom electrode and the firstinsulating film. The adhesive layer may contact with the bottomelectrode and with the first insulating film. The adhesive layer mayhave adhesiveness to the bottom electrode and to the first insulatingfilm.

In accordance with a third aspect of the present invention, a method offorming a semiconductor device with a capacitor may include, but is notlimited to the following processes. A first hole is formed in a firstinsulating layer that includes a first insulating film. The firstinsulating film has a first portion that is exposed to the first hole.The first portion is modified to form an intermediate layer thatadjacent to the first insulating film. The intermediate layer is exposedto the first hole. The intermediate layer has adhesiveness to the firstinsulating film. An adhesive layer is formed which contacts with theintermediate layer and with bottom and side walls of the first hole. Theadhesive layer has adhesiveness to the intermediate layer. A bottomelectrode is formed which contacts with the adhesive layer. The adhesivelayer has adhesiveness to the bottom electrode. A capacitive insulatingfilm is formed which contacts with the bottom electrode. A top electrodeis formed which contacts with the contacts with the capacitiveinsulating film.

In accordance with a fourth aspect of the present invention, a method offorming a semiconductor device with a capacitor may include, but is notlimited to, the following processes. A first hole is formed in a firstinsulating layer that includes a first insulating film. The firstinsulating film has a first portion that is exposed to the first hole.An adhesive layer is formed which contacts with the first portion andwith bottom and side walls of the first hole. The adhesive layer hasadhesiveness to the first portion. A bottom electrode is formed whichcontacts with the adhesive layer. The adhesive layer has adhesiveness tothe bottom electrode. A capacitive insulating film is formed whichcontacts with the bottom electrode. A top electrode is formed whichcontacts with the contacts with the capacitive insulating film.

These and other objects, features, aspects, and advantages of thepresent invention will become apparent to those skilled in the art fromthe following detailed descriptions taken in conjunction with theaccompanying drawings, illustrating the embodiments of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the attached drawings which form a part of thisoriginal disclosure:

FIG. 1 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a first preferredembodiment of the present invention;

FIG.2 is a fragmentary enlarged cross sectional view illustrating acapacitor structure included in a memory cell in the semiconductordevice of FIG. 1;

FIG. 3 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step involved in a method offorming the semiconductor memory device of FIGS. 1 and 2 in accordancewith the first embodiment of the present invention;

FIG. 4 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.3, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 5 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.4, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 6 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.5, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 7 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.6, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 8 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.7, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 9 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.8, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 10 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.9, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 11 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.10, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 12 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.11, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 13 is a fragmentary cross sectional elevation views illustrating asemiconductor memory device in a sequential step, after the step of FIG.12, involved in a method of forming the semiconductor memory device ofFIGS. 1 and 2 in accordance with the first embodiment of the presentinvention;

FIG. 14 is a photograph showing a fragmentary cross section of aportion, marked by “k” in FIG. 2, of the capacitor included in thesemiconductor memory device by the above-described series of processesof FIGS. 2-13 in accordance with the first embodiment of the presentinvention;

FIG. 15 is a photograph showing a fragmentary cross section of a portionof the capacitor in the absence of any adhesive layers between them inaccordance with a comparative example to the first embodiment of thepresent invention;

FIG. 16A is a diagram showing measured time zero dielectric breakdowncharacteristics of the capacitors of the first embodiment of the presentinvention and the comparative example;

FIG. 16B is a diagram showing measured time zero dielectric breakdowncharacteristics of the capacitors of the first embodiment of the presentinvention and the comparative example;

FIG. 17 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a second preferredembodiment of the present invention;

FIG. 18 is a fragmentary enlarged cross sectional view illustrating acapacitor structure included in a memory cell in the semiconductordevice of FIG. 17;

FIG. 19 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step involved in a method offorming the semiconductor memory device of FIGS. 17 and 18 in accordancewith the second embodiment of the present invention;

FIG. 20 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.19, involved in a method of forming the semiconductor memory device ofFIGS. 17 and 18 in accordance with the second embodiment of the presentinvention;

FIG. 21 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.20, involved in a method of forming the semiconductor memory device ofFIGS. 17 and 18 in accordance with the second embodiment of the presentinvention;

FIG. 22 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.21, involved in a method of forming the semiconductor memory device ofFIGS. 17 and 18 in accordance with the second embodiment of the presentinvention;

FIG. 23 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a third preferredembodiment of the present invention;

FIG. 24 is a fragmentary enlarged cross sectional view illustrating acapacitor structure with a pedestal bottom electrode which is includedin a memory cell in the semiconductor device of FIG. 23;

FIG. 25 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step involved in a method offorming the semiconductor memory device of FIGS. 23 and 24 in accordancewith the third embodiment of the present invention;

FIG. 26 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.25, involved in a method of forming the semiconductor memory device ofFIGS. 23 and 24 in accordance with the third embodiment of the presentinvention;

FIG. 27 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.26, involved in a method of forming the semiconductor memory device ofFIGS. 23 and 24 in accordance with the third embodiment of the presentinvention;

FIG. 28 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.27, involved in a method of forming the semiconductor memory device ofFIGS. 23 and 24 in accordance with the third embodiment of the presentinvention; and

FIG. 29 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in a sequential step, after the step of FIG.28, involved in a method of forming the semiconductor memory device ofFIGS. 23 and 24 in accordance with the third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with a first aspect of the present invention, asemiconductor device may include, but is not limited to, a firstinsulating layer, a capacitor, an adhesive layer, and an intermediatelayer. The first insulating layer may include a first insulating film.The first insulating layered structure has a first hole. The capacitoris disposed in the first hole. The capacitor may include bottom and topelectrodes and a capacitive insulating film. The capacitive insulatingfilm is sandwiched between the bottom and top electrodes. The adhesivelayer contacts with the bottom electrode. The adhesive layer hasadhesiveness to the bottom electrode. The intermediate layer isinterposed between the adhesive layer and the first insulating film. Theintermediate layer contacts with the adhesive layer and with the firstinsulating film. The intermediate layer has adhesiveness to the adhesivelayer and to the first insulating film.

The adhesive layer has adhesiveness to the bottom electrode. Theintermediate layer has adhesiveness to the adhesive layer. Theintermediate layer also has adhesiveness to the first insulating film.The combination of the adhesive layer and the intermediate layerprovides adhesiveness between the bottom electrode and the firstinsulating film. This can prevent the bottom electrode from beingfalling down or being peeled or deformed by the process for forming thecapacitor. Typically, the process for forming the capacitor may include,but is not limited to, a thermal process or a chemical process. This canensure high reliability to the semiconductor device.

In some cases, the bottom electrode may be made of nitride containing afirst metal. The adhesive layer may be made of one of the first metaland oxide containing the first metal. The intermediate layer may be madeof oxynitride containing a first semiconductor. The first insulatingfilm may be made of nitride containing the first semiconductor. In somecases, the bottom electrode may cover bottom and side walls of the firsthole.

In some cases, the intermediate layer may be a modified portion of thefirst insulating film. The modified portion is adjacent to the adhesivelayer. The intermediate layer can be formed by modifying a portion ofthe first insulating film to provide adhesiveness, after the firstinsulating film has been used as an etching stopper.

In some cases, the first semiconductor may be silicon, and the firstinsulating film may be made of silicon nitride. The modified portion ofthe first insulating film may be made of silicon oxynitride.

In some cases, the first insulating layer may include, but is notlimited to, a stack of a silicon oxide film and the first insulatingfilm. The silicon oxide film extends over the first insulating film. Thefirst hole penetrates the stack. This structure may allow increasing thedepth of the first hole. The increase in the depth of the first holeincreases the capacity of the capacitor. If no etching stopper is used,increasing the depth of the first hole makes it difficult to realize aprecise control of the depth of the first hole. As described above, theintermediate layer can be formed by modifying a portion of the firstinsulating film to provide adhesiveness, after the first insulating filmhas been used as an etching stopper. This makes it easy to realize aprecise control of the depth of the first hole.

In some cases, the first metal may be titanium, the adhesive layer mayinclude one of titanium and titanium oxide, and the bottom electrode mayinclude titanium nitride. Silicon oxynitride (SiON) has adhesiveness toboth titanium oxide (TiO) and silicon nitride (SiN). Titanium oxide(TiO) has adhesiveness to titanium nitride. The adhesive layer hasadhesiveness to the bottom electrode. The intermediate layer hasadhesiveness to the adhesive layer. The intermediate layer also hasadhesiveness to the first insulating film. The combination of theadhesive layer and the intermediate layer provides adhesiveness betweenthe bottom electrode and the first insulating film. This can prevent thebottom electrode from being falling down or being peeled or deformed bythe process for forming the capacitor. Typically, the process forforming the capacitor may include, but is not limited to, a thermalprocess or a chemical process. This can ensure high reliability to thesemiconductor device.

The semiconductor device may further include, but is not limited to, atleast one polysilicon plug, at least one titanium silicide layer, and atleast one memory cell switching transistor. The at least one titaniumsilicide layer is present between the at least one polysilicon plug andthe bottom electrode. The titanium silicide layer contacts with the atleast one polysilicon plug and with the bottom electrode. The at leastone memory cell switching transistor is electrically connected throughthe at least one polysilicon plug and the titanium silicide layer to thebottom electrode. This structure reduces the resistance between thecapacitor and the at least one memory cell switching transistor. Thismay improve the performance of the semiconductor device.

In some cases, the bottom electrode may have one of a cylinder shape anda modified cylinder shape. The modified cylinder shape is athree-dimensional shape that has coaxial inside and outside cylinderwalls and a torus bottom wall that communicates between the coaxialinside and outside cylinder walls. The stack of the capacitiveinsulating film and the top electrode covers at least one of opposingsurfaces of the bottom electrode. This structure provides increasedcapacity to the capacitor.

In some cases, the bottom electrode may have a pedestal shape and mayfill the first hole. The stack of the capacitive insulating film and thetop electrode covers an outside surface of the bottom electrode. Thisstructure provides increased capacity to the capacitor.

In accordance with a second aspect of the present invention, asemiconductor device may include, but is not limited to, a firstinsulating layer, a capacitor, and an adhesive layer. The firstinsulating layer may include a first insulating film, the firstinsulating layered structure having a first hole. The capacitor may bedisposed in the first hole. The capacitor may include, but is notlimited to, bottom and top electrodes and a capacitive insulating filmthat is sandwiched between the bottom and top electrodes. The adhesivelayer may be interposed between the bottom electrode and the firstinsulating film. The adhesive layer may contact with the bottomelectrode and with the first insulating film. The adhesive layer mayhave adhesiveness to the bottom electrode and to the first insulatingfilm.

The adhesive layer has adhesiveness to the bottom electrode and to thefirst insulating film. The adhesive layer provides adhesiveness betweenthe bottom electrode and the first insulating film. This can prevent thebottom electrode from being falling down or being peeled or deformed bythe process for forming the capacitor. Typically, the process forforming the capacitor may include, but is not limited to, a thermalprocess or a chemical process. This can ensure high reliability to thesemiconductor device.

In some cases, the bottom electrode may be made of nitride containing afirst metal. The adhesive layer may be made of one of the first metaland oxide containing the first metal. The first insulating film may bemade of oxynitride containing a first semiconductor. In some cases, thebottom electrode covers bottom and side walls of the first hole.

In some cases, the first semiconductor is silicon, and the firstinsulating film comprises silicon oxynitride. The adhesive layerprovides adhesiveness between the bottom electrode and the firstinsulating film.

In some cases, the first insulating layer may include a stack of asilicon oxide film and the first insulating film. The silicon oxide filmmay extend over the first insulating film.

In some cases, the first metal may be titanium, and the adhesive layermay be made of one of titanium and titanium oxide, and the bottomelectrode comprises titanium nitride. Silicon oxynitride (SiON) hasadhesiveness to titanium oxide (TiO). Titanium oxide (TiO) hasadhesiveness to titanium nitride. The adhesive layer has adhesiveness tothe bottom electrode. The adhesive layer has adhesiveness to the bottomelectrode and to the first insulating film. The adhesive layer providesadhesiveness between the bottom electrode and the first insulating film.This can prevent the bottom electrode from being falling down or beingpeeled or deformed by the process for forming the capacitor. Typically,the process for forming the capacitor may include, but is not limitedto, a thermal process or a chemical process. This can ensure highreliability to the semiconductor device.

The semiconductor device may further include, but is not limited to, atleast one polysilicon plug, at least one titanium silicide layer, and atleast one memory cell switching transistor. The at least one titaniumsilicide layer is present between the at least one polysilicon plug andthe bottom electrode. The titanium silicide layer contacts with the atleast one polysilicon plug and with the bottom electrode. The at leastone memory cell switching transistor is electrically connected throughthe at least one polysilicon plug and the titanium silicide layer to thebottom electrode. This structure reduces the resistance between thecapacitor and the at least one memory cell switching transistor. Thismay improve the performance of the semiconductor device.

In some cases, the bottom electrode may have one of a cylinder shape anda modified cylinder shape. The modified cylinder shape is athree-dimensional shape that has coaxial inside and outside cylinderwalls and a torus bottom wall that communicates between the coaxialinside and outside cylinder walls. The stack of the capacitiveinsulating film and the top electrode covers at least one of opposingsurfaces of the bottom electrode. This structure provides increasedcapacity to the capacitor.

In some cases, the bottom electrode may have a pedestal shape and mayfill the first hole. The stack of the capacitive insulating film and thetop electrode covers an outside surface of the bottom electrode. Thisstructure provides increased capacity to the capacitor.

In accordance with a third aspect of the present invention, a method offorming a semiconductor device with a capacitor may include, but is notlimited to the following processes. A first hole is formed in a firstinsulating layer that includes a first insulating film. The firstinsulating film has a first portion that is exposed to the first hole.The first portion is modified to form an intermediate layer thatadjacent to the first insulating film. The intermediate layer is exposedto the first hole. The intermediate layer has adhesiveness to the firstinsulating film. An adhesive layer is formed which contacts with theintermediate layer and with bottom and side walls of the first hole. Theadhesive layer has adhesiveness to the intermediate layer. A bottomelectrode is formed which contacts with the adhesive layer. The adhesivelayer has adhesiveness to the bottom electrode. A capacitive insulatingfilm is formed which contacts with the bottom electrode. A top electrodeis formed which contacts with the contacts with the capacitiveinsulating film.

The adhesive layer has adhesiveness to the bottom electrode. Theintermediate layer has adhesiveness to the adhesive layer. Theintermediate layer also has adhesiveness to the first insulating film.The combination of the adhesive layer and the intermediate layerprovides adhesiveness between the bottom electrode and the firstinsulating film. This can prevent the bottom electrode from beingfalling down or being peeled or deformed by the process for forming thecapacitor. Typically, the process for forming the capacitor may include,but is not limited to, a thermal process or a chemical process. This canensure high reliability to the semiconductor device.

In some cases, the bottom electrode may be made of nitride containing afirst metal. The adhesive layer may be made of one of the first metaland oxide containing the first metal. The intermediate layer may be madeof oxynitride containing a first semiconductor. The first insulatingfilm may be made of nitride containing the first semiconductor.

In some cases, the first semiconductor may be silicon, and the firstinsulating film may be made of silicon nitride. The process formodifying the first portion may be the process for modifying siliconnitride of the first portion into silicon oxynitride. The intermediatelayer can be formed by modifying a portion of the first insulating filmto provide adhesiveness, after the first insulating film has been usedas an etching stopper.

In some cases, the process for forming the first hole may be the processfor forming the first hole that penetrate a stack of a silicon oxidefilm and the first insulating film of silicon nitride. The silicon oxidefilm extends over the first insulating film. This structure may allowincreasing the depth of the first hole. The increase in the depth of thefirst hole increases the capacity of the capacitor. If no etchingstopper is used, increasing the depth of the first hole makes itdifficult to realize a precise control of the depth of the first hole.As described above, the intermediate layer can be formed by modifying aportion of the first insulating film to provide adhesiveness, after thefirst insulating film has been used as an etching stopper. This makes iteasy to realize a precise control of the depth of the first hole.

In some cases, the process for forming the first hole may include, butis not limited to, the following processes. A first etching process iscarried out for selectively etching the silicon oxide film under a firstcondition that a first etching rate of the first insulating film ofsilicon nitride is higher than a second etching rate of the siliconoxide film. A second etching process is carried out for selectivelyetching the first insulating film of silicon nitride under a secondcondition that a third etching rate of the silicon oxide film is higherthan a fourth etching rate of the first insulating film of siliconnitride. This makes it easy to realize a precise control of the depth ofthe first hole.

In some cases, the method may further include the following process. Atleast one polysilicon plug is formed in a second insulating layer thatunderlies the first insulating layer. The process for forming the firsthole may be the process for forming the first hole so that a secondportion of the at least one polysilicon plug is exposed to the firsthole. The process for modifying the first portion may be the process formodifying the first and second portion to respectively form theintermediate layer and a silicon oxide portion of the at least onepolysilicon plug. The silicon oxide portion is adjacent to the firsthole and also adjacent to the at least one polysilicon plug. The methodmay further include the following process. The silicon oxide portion isremoved before forming an adhesive layer. This can ensure electricalconductivity between the capacitor and the memory cell switchingtransistor.

In some cases, the process for forming the adhesive layer may be theprocess for carrying out a chemical vapor deposition using a titaniumtetrachloride gas to form the adhesive layer and a titanium silicidelayer on the at least one polysilicon plug. This reduces the resistancebetween the capacitor and the at least one memory cell switchingtransistor. This may improve the performance of the semiconductordevice.

In some cases, the method may further include the following process. Aperipheral portion of the first insulating layer is removed afterforming the bottom electrode, thereby forming a gap between the firstinsulating layer and the adhesive layer that covers a surface of thebottom electrode. The peripheral portion surrounds and is adjacent tothe adhesive layer and the bottom electrode. A nitration process may becarried out for nitrating the adhesive layer to form a titanium nitridefilm that covers the surface of the bottom electrode. The adhesive layeris modified into the conductive layer. This increases the capacity ofthe capacitor. This also improves the reliability of the capacitor. Thisfurther prevents any leakage of current from the bottom electrode.

In some cases, the process for removing the peripheral portion may becarried out using the first insulating film of silicon nitride as anetching stopper, thereby increasing the controllability of the etchingdepth.

In accordance with a fourth aspect of the present invention, a method offorming a semiconductor device with a capacitor may include, but is notlimited to, the following processes. A first hole is formed in a firstinsulating layer that includes a first insulating film. The firstinsulating film has a first portion that is exposed to the first hole.An adhesive layer is formed which contacts with the first portion andwith bottom and side walls of the first hole. The adhesive layer hasadhesiveness to the first portion. A bottom electrode is formed whichcontacts with the adhesive layer. The adhesive layer has adhesiveness tothe bottom electrode. A capacitive insulating film is formed whichcontacts with the bottom electrode. A top electrode is formed whichcontacts with the contacts with the capacitive insulating film.

The adhesive layer has adhesiveness to the bottom electrode and to thefirst insulating film. The adhesive layer provides adhesiveness betweenthe bottom electrode and the first insulating film. This can prevent thebottom electrode from being falling down or being peeled or deformed bythe process for forming the capacitor. Typically, the process forforming the capacitor may include, but is not limited to, a thermalprocess or a chemical process. This can ensure high reliability to thesemiconductor device.

In some cases, the bottom electrode may be made of nitride containing afirst metal. The adhesive layer may be made of one of the first metaland oxide containing the first metal. The first insulating film may bemade of oxynitride containing a first semiconductor.

In some cases, the method may further include, but is not limited to,the following processes. At least one polysilicon plug is formed in asecond insulating layer that underlies the first insulating layer. Theprocess for forming the first hole may be the process for forming thefirst hole so that a second portion of the at least one polysilicon plugis exposed to the first hole. The process for forming the adhesive layermay be the process for carrying out a chemical vapor deposition using atitanium tetrachloride gas to form the adhesive layer and a titaniumsilicide layer on the at least one polysilicon plug. This reduces theresistance between the capacitor and the at least one memory cellswitching transistor. This may improve the performance of thesemiconductor device.

In some cases, the method may further include the following process. Aperipheral portion of the first insulating layer is removed afterforming the bottom electrode, thereby forming a gap between the firstinsulating layer and the adhesive layer that covers a surface of thebottom electrode. The peripheral portion surrounds and is adjacent tothe adhesive layer and the bottom electrode. A nitration process may becarried out for nitrating the adhesive layer to form a titanium nitridefilm that covers the surface of the bottom electrode. The adhesive layeris modified into the conductive layer. This increases the capacity ofthe capacitor. This also improves the reliability of the capacitor. Thisfurther prevents any leakage of current from the bottom electrode.

In some cases, the process for removing the peripheral portion may becarried out using the first insulating film of silicon nitride as anetching stopper, thereby increasing the controllability of the etchingdepth.

The adhesive layer alone or in combination with the intermediate layermay provide adhesiveness between the first insulating film the bottomelectrode of the capacitor. This can improve the reliability of thecapacitor, and further improve the semiconductor device such as asemiconductor memory device, for example, DRAMs.

Selected embodiments of the present invention will now be described withreference to the drawings. It will be apparent to those skilled in theart from this disclosure that the following descriptions of theembodiments of the present invention are provided for illustration onlyand not for the purpose of limiting the invention as defined by theappended claims and their equivalents.

First Embodiment

The first embodiment provides a semiconductor memory device including ametal-insulator-metal capacitor and a method of forming the same. Thedescriptions of the first embodiment will be made with reference toFIGS. 1-16.

(1) Semiconductor Memory Device and Capacitor Structure:

FIG. 1 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a first preferredembodiment of the present invention. The semiconductor memory deviceincludes a memory cell area 100 and a peripheral circuit area 200, whichare adjacent to each other. The memory cell area 100 has a memory cell.The peripheral circuit area 200 has a peripheral circuit. Thesemiconductor memory device has a silicon substrate 10 that has a mainface. An isolating film 2 such as a local oxidation of silicon film isdisposed on the main face of the silicon substrate 10.

In the memory cell area 100, the isolation film 2 defines a first activeregion of the silicon substrate 10, wherein the first active region issurrounded by the isolation film 2. In the memory cell area 100, a pairof switching transistors is disposed on the first active region of thesilicon substrate 10. The switching transistors will be hereinafterreferred to as memory cell transistors. Each of the memory celltransistors includes a gate insulating film 3, a gate electrode 4, anddiffusion layers 5 and 6 that perform as source and drain regions. Thegate insulating film 3 is disposed on the main face of the first activeregion of the silicon substrate 10 in the memory cell area 100. The gateelectrode 4 is provided on the gate insulating film 3. The diffusionlayers 5 and 6 performing as the source and drain regions areselectively provided in the first active region of the silicon substrate10 in the memory cell area 100. The diffusion layer 6 is the layercommon to the paired switching transistors. Each of the gate electrodes4 is covered by an insulating film 31.

In the peripheral circuit area 200, the isolation film 2 defines asecond active region of the silicon substrate 10, wherein the secondactive region is surrounded by the isolation film 2. In the peripheralcircuit area 200, a transistor for peripheral circuit, which will behereinafter referred to as “peripheral circuit transistor”, is disposedon the second active region of the silicon substrate 10. The peripheralcircuit transistor includes a gate insulating film 3, a gate electrode,and a pair of diffusion layers 7 and 7 a that perform as source anddrain regions. The gate insulating film 3 is disposed on the main faceof the first active region of the silicon substrate 10 in the memorycell area 100. The gate electrode 4 is provided on the gate insulatingfilm 3. The diffusion layers 7 and 7 a performing as the source anddrain regions are selectively provided in the second active region ofthe silicon substrate 10 in the peripheral circuit area 200. The gateelectrode 4 is covered by an insulating film 31.

Over the memory cell area 100 and the peripheral circuit area 200, afirst inter-layer insulator 21 is disposed. The first inter-layerinsulator 21 extends over the first and second active regions and theisolation film 2. The first inter-layer insulator 21 embeds the memorycell transistors and the peripheral circuit transistor.

In the memory cell area 100, the first inter-layer insulator 21 hasfirst to third contact holes. The first contact hole communicates withthe diffusion layer 6. The second and third contact holes communicatewith the diffusion layers 5. The first contact hole is filled with apolysilicon plug 11 a. The second and third contact holes are filledwith polysilicon plugs 11. The polysilicon plug 11 a contacts with thediffusion layer 6. The polysilicon plugs 11 contact with the diffusionlayers 5. A bit-line 8 is provided on the first inter-layer insulator21. The bit-line 8 may be realized by a tungsten film. The bit-line 8contacts with the top of the polysilicon plug 11 a. The bit-line 8 iselectrically connected through the polysilicon plug 11 a to thediffusion layer 6.

In the peripheral circuit area 200, the first inter-layer insulator 21further has fourth and fifth contact holes. The fourth and fifth contactholes communicate with the diffusion layers 7 and 7 a. The fourth andfifth contact holes are filled with metal plugs 41 and 41 a. The metalplugs 41 and 41 a contact with the diffusion layers 7 and 7 a. Afirst-level interconnection 8 a is provided on the first inter-layerinsulator 21. The first-level interconnection 8 a may be realized by atungsten film. The first-level interconnection 8 a is electricallyconnected through the metal plug 41 a to the diffusion layer 7 a.

Over the memory cell area 100 and the peripheral circuit area 200, asecond inter-layer insulator 22 is disposed. The second inter-layerinsulator 22 extends over the first inter-layer insulator 21, thepolysilicon plugs 11 and 11 a, and the metal plugs 41 and 41 a, as wellas over the bit line 8 and the first-level interconnection 8 a. Thesecond inter-layer insulator 22 embeds the bit line 8 and thefirst-level interconnection 8 a.

In the memory cell area 100, the second inter-layer insulator 22 hasfirst and second through holes which communicate with the polysiliconplugs 11. The first and second through holes except for these upperportions are filled with polysilicon plugs 12. The upper portions of thefirst and second through holes are filled with titanium silicide films50. The titanium silicide films 50 contact with the polysilicon plugs12. The polysilicon plugs 12 contact with the polysilicon plugs 11 whichfurther contact with the diffusion layers 5. Thus, the titanium silicidefilms 50 are eclectically connected through the polysilicon plugs 12 and11 to the diffusion layers 5 of the memory cell transistors.

Over the memory cell area 100 and the peripheral circuit area 200, athird inter-layer insulator 32 is disposed on the second inter-layerinsulator 22 and on the titanium silicide films 50. The thirdinter-layer insulator 32 can be realized by a silicon nitride film. Afourth inter-layer insulator 23 is disposed on the third inter-layerinsulator 32. Each of the first, second and fourth inter-layerinsulators 21, 22 and 23 can be realized by a silicon oxide film.

In the memory cell area 100, a hole 96 is formed in the stack of thethird and fourth inter-layer insulators 32 and 23. The hole 96 will behereinafter referred to as a capacitor hole 96. The capacitor hole 96may be modified-cylinder-shaped. The modified-cylinder-shape maytypically be a three-dimensional shape that has coaxial inside andoutside cylinder walls and a torus bottom that communicates between thecoaxial inside and outside cylinder walls. In plan view, the capacitorhole 96 has a torus shape. The capacitor hole 96 penetrates the stack ofthe third and fourth inter-layer insulators 32 and 23. The capacitorhole 96 communicates with the titanium silicide films 50 in the firstand second through holes.

A capacitor 54 is disposed in the capacitor hole 96. The capacitor 54 iselectrically connected through the titanium silicide films 50, thepolysilicon plugs 12 and 11 to the diffusion layers 5 of the memory celltransistors 5. When the capacitor hole 96 has themodified-cylinder-shape, the capacitor 54 also has themodified-cylinder-shape. The modified-cylinder-shape may typically be athree-dimensional shape that has coaxial inside and outside cylinderwalls and a torus bottom that communicates between the coaxial insideand outside cylinder walls.

FIG. 2 is a fragmentary enlarged cross sectional view illustrating acapacitor structure included in a memory cell in the semiconductordevice of FIG. 1. The capacitor 54 may have a multi-layered structurethat includes adhesive layers 81 and 81 a, a bottom electrode 51, acapacitive insulating film 52, and a top electrode 53. The multi-layeredstructure extends along the side and bottom walls of the capacitor hole96 of the modified-cylinder-shape as well as over an adjacent topsurface portion of the fourth inter-layer insulator 32 and 23. Theadjacent top surface portion of the fourth inter-layer insulator 32 and23 is adjacent to the capacitor hole 96.

The multi-layered structure may includes the adhesive layers 81 and 81a, the bottom electrode 51, the capacitive insulating film 52, and thetop electrode 53. The adhesive layers 81 extend on the side and bottomwalls of the capacitor hole 96 of the modified-cylinder-shape. Theadhesive layer 81 a extends on the lower portion of the side walls ofthe capacitor hole 96 of the modified-cylinder-shape. The adhesive layer81 a of titanium oxide contacts with a silicon oxynitride film 82.Further, the silicon oxynitride film 82 contacts with the side edge ofthe third inter-layer insulator 32 of silicon nitride. The adhesivelayer 81 a and the silicon oxynitride film 82 have substantially thesame level as the third inter-layer insulator 32. The bottom wall of thecapacitor hole 96 has a torus shape. The adhesive layer 81 on the bottomwall of the capacitor hole 96 has openings through which the titaniumsilicide films 50 are shown. The adhesive layers 81 and 81 a may berealized by a titanium oxide film. The adhesive layers 81 contact withthe second and fourth inter-layer insulators 22 and 23 of silicon oxide.

The bottom electrode 51 extends on the adhesive layers 81 and 81 a andthe top surfaces of the titanium silicide films 50. Namely, the bottomelectrode 51 contacts with the adhesive layers 81 and 81 a and the topsurfaces of the titanium silicide films 50. The bottom electrode 51extends along the side and bottom walls of the capacitor hole 96 of themodified-cylinder-shape. The bottom electrode 51 may be realized by afirst titanium nitride film.

The capacitive insulating film 52 extends on the bottom electrode 51.Namely, the capacitive insulating film 52 contacts the bottom electrode51. The capacitive insulating film 52 extends along the side and bottomwalls of the capacitor hole 96 of the modified-cylinder-shape. Thecapacitive insulating film 52 may be realized by an aluminum oxide film.The thickness of the capacitive insulating film 52 may typically be, butis not limited to, 6 nanometers.

The top electrode 53 extends on the capacitive insulating film 52.Namely, the top electrode 53 contacts with the capacitive insulatingfilm 52. The top electrode 53 extends along the side and bottom walls ofthe capacitor hole 96 of the modified-cylinder-shape. The top electrode53 may be realized by a second titanium nitride film. The thickness ofthe top electrode 53 may typically be, but is not limited to, 15nanometers.

Thus, the silicon oxynitride film 82 is horizontally adjacent to thesilicon nitride inter-layer insulator 32. The titanium oxide adhesivelayer 81 a is adjacent to the silicon oxynitride film 82. The siliconoxynitride film 82 is interposed between the silicon nitride inter-layerinsulator 32 and the titanium oxide adhesive layer 81 a. The bottomportion of the titanium nitride bottom electrode 51 is horizontallyadjacent to the titanium oxide adhesive layer 81 a. The titanium oxideadhesive layer 81 a is interposed between the silicon oxynitride film 82and the bottom portion of the titanium nitride bottom electrode 51.

The bottom electrode 51 performs as an electrode of the capacitor 54.The bottom electrode 51 has an outer surface that adheres to theadhesive layers 81 and 81 a. The adhesive layer 81 adheres to the fourthinter-layer insulator 23 of silicon oxide. The adhesive layer 81 aadheres to the silicon oxynitride film 82. The silicon oxynitride film82 adheres to the third inter-layer insulator 32 of silicon nitride. Thebottom electrode 51 has the bottom portion which partially contacts withthe titanium silicide films 50.

With reference back to FIG. 1, the titanium silicide films 50 contactwith the polysilicon plugs 12. The polysilicon plugs 12 contact with thepolysilicon plugs 11. The polysilicon plugs 11 contact with thediffusion layers 5 of the memory cell transistors. Namely, the bottomelectrode 51 of the capacitor 54 is electrically connected to thediffusion layers 5 of the memory cell transistors.

Over the memory cell area 100 and the peripheral circuit area 200, afifth inter-layer insulator 24 is disposed on the top electrode 53 ofthe capacitor 54 and on the fourth inter-layer insulator 24. The fifthinter-layer insulator 24 can be realized by a silicon oxide film.

In the peripheral circuit area 200, third and fourth through holes areformed in the stack of the second, third, fourth and fifth inter-layers22, 32, 23, and 24. The third through hole communicates with the top ofthe metal plug 41. The metal plug 41 contacts with the diffusion layer7. The fourth through hole communicates with the top surface of thefirst-level interconnection 8 a. The first-level interconnection 8 acontacts with the top of the metal plug 41 a. The metal plug 41 acontacts with the diffusion layer 7 a. The third and fourth throughholes are filled with first and second contact plugs 42 and 43,respectively. The first and second contact plugs 42 and 43 contact withthe metal plug 41 and the first-level interconnection 8 a. The firstcontact plug 43 is electrically connected through the metal plug 41 tothe diffusion layer 7 of the peripheral circuit transistor. The secondcontact plug 44 is electrically connected through the first-levelinterconnection 8 a and the metal plug 41 a to the diffusion layer 7 aof the peripheral circuit transistor.

On the boundary between the memory cell area 100 and the peripheralcircuit area 200, a fifth through hole is formed in the fifthinter-layer insulator 24. The fifth through hole communicates with thetop electrode 53 of the capacitor 54. The fifth through hole is filledwith a third contact plug 44. The third contact plug 44 contacts withthe top electrode 53 of the capacitor 54. A second-level interconnection61 is disposed on the fifth inter-layer insulator 24 so that thesecond-level interconnection 61 contacts with the second and thirdcontact plugs 43 and 44. Namely, the second-level interconnection 61electrically connects between the first and third contact plugs 43 and44. An additional second-level interconnection 61 a is disposed on thefifth inter-layer insulator 24 so that the additional second-levelinterconnection 61 a contacts with the first contact plug 42.

The bit line 8 is electrically connected through the polysilicon plug 11a to the memory cell transistors. The memory cell transistors areelectrically connected through the polysilicon plugs 11 and 12 to thecapacitor 54. The capacitor 54 is electrically connected to theperipheral circuit transistor through the third contact plug 44, thesecond-level interconnection 61, the second contact plug 43, and themetal plug 41. The peripheral circuit transistor is electricallyconnected to a peripheral circuit through the metal plug 41 a, the firstlevel interconnection 8 a, the first contact plug 42, and the additionalsecond-level interconnection 61 a. In other words, the peripheralcircuit transistor performs as a switch between the top electrode 53 ofthe capacitor 54 of the memory cell and the peripheral circuit. Thememory cell transistors perform as another switch between the bit line 8and the bottom electrode 51 of the capacitor 54 of the memory cell.

(2) Method of Forming Semiconductor Memory Device and Capacitor:

A method of forming the semiconductor memory device of FIG. 1 includingthe memory cell capacitor of FIG. 2 will be described. FIGS. 3 through13 are fragmentary cross sectional elevation views illustratingsemiconductor memory devices in sequential steps involved in a method offorming the semiconductor memory device of FIGS. 1 and 2 in accordancewith the first embodiment of the present invention.

With reference to FIG. 3, a silicon substrate 10 with a main face isprepared. An isolating film 2 such as a local oxidation of silicon filmis formed on the main face of the silicon substrate 10 so that theisolating film 2 defines first and second active regions of the siliconsubstrate 10 in the memory cell area 100 and the peripheral circuit area200 shown in FIG. 1. The first and second active regions are surroundedby the isolating film 2. First and second gate structures are formed onthe first active region, while a third gate structure is formed on thesecond active region. Each of the gate structure includes a gateinsulating film 3, a gate electrode 4, and an insulating film 31. Theprocesses for forming the first to third gate structures may be theknown processes. Diffusion layers 5 and 6 that perform as source anddrain regions are formed in the first active region, while diffusionlayers 7 and 7 a that perform as source and drain regions are formed inthe second active region. The processes for forming the diffusion layers5, 6, 7 and 7 a may be the known processes. As a result, a pair ofmemory cell transistors is formed in the first active region, while aperipheral circuit transistor is formed in the second active region.

A first inter-layer insulator 21 is formed over the memory cell area 100and the peripheral circuit area 200. Namely, the first inter-layerinsulator 21 is formed over the first and second active regions and theisolation film 2. The first inter-layer insulator 21 embeds the memorycell transistors and the peripheral circuit transistor.

In the memory cell area 100, first to third contact holes are formed inthe first inter-layer insulator 21, so that the first contact holecommunicates with the diffusion layer 6, and the second and thirdcontact holes communicate with the diffusion layers 5. In the peripheralcircuit area 200, fourth and fifth contact holes are formed in the firstinter-layer insulator 21, so that the fourth and fifth contact holescommunicate with the diffusion layers 7 and 7 a. Deposition of apolysilicon film and subsequent etch-back process is carried out. Apolysilicon plug 11 a is formed in the first contact hole, whilepolysilicon plugs 11 are formed in the second and third contact holes.The polysilicon plug 11 a contacts with the diffusion layer 6. Thepolysilicon plugs 11 contact with the diffusion layers 5. Further,deposition of a metal film and subsequent etch-back process is carriedout. Metal plugs 41 and 41 a are formed in the fourth and fifth contactholes. The metal plugs 41 and 41 a contact with the diffusion layers 7and 7 a.

A bit-line 8 and a first-level interconnection 8 a are formed on thefirst inter-layer insulator 21 so that the bit-line 8 contacts with thetop of the polysilicon plug 11 a and the first-level interconnection 8 acontacts with the metal plug 41 a. The bit-line 8 is electricallyconnected through the polysilicon plug 11 a to the diffusion layer 6.The first-level interconnection 8 a is electrically connected throughthe metal plug 41 a to the diffusion layer 7 a. The bit-line 8 and thefirst-level interconnection 8 a may be realized by a tungsten film.

Over the memory cell area 100 and the peripheral circuit area 200, asecond inter-layer insulator 22 is formed over the first inter-layerinsulator 21, the polysilicon plugs 11 and 11 a, and the metal plugs 41and 41 a, as well as over the bit line 8 and the first-levelinterconnection 8 a. The second inter-layer insulator 22 embeds the bitline 8 and the first-level interconnection 8 a. The second inter-layerinsulator 22 can be realized by a silicon oxide film.

In the memory cell area 100, first and second through holes are formedin the second inter-layer insulator 22 so that the first and secondthrough holes communicate with the polysilicon plugs 11. Deposition of apolysilicon film and subsequent etch-back process is carried out so thatpolysilicon plugs 12 are formed in the first and second through holes ofthe second inter-layer insulator 22. The polysilicon plugs 12 contactwith the polysilicon plugs 11 which further contact with the diffusionlayers 5. Thus, the polysilicon plugs 12 are eclectically connectedthrough the polysilicon plugs 11 to the diffusion layers 5 of the memorycell transistors.

With reference to FIG. 4, over the memory cell area 100 and theperipheral circuit area 200, a third inter-layer insulator 32 is formedon the second inter-layer insulator 22 and on the titanium silicidefilms 50. The third inter-layer insulator 32 can be realized by asilicon nitride film. Further, a fourth inter-layer insulator 23 isformed on the third inter-layer insulator 32. The fourth inter-layerinsulator 23 can be realized by a silicon oxide film. The thickness ofthe fourth inter-layer insulator 23 may typically be, but is not limitedto, 3 micrometers.

With reference to FIG. 5, in the memory cell area 100, a capacitor hole96 is formed in the stack of the third and fourth inter-layer insulators32 and 23. The capacitor hole 96 may be modified-cylinder-shaped. Inplan view, the capacitor hole 96 has a torus shape. The capacitor hole96 penetrates the stack of the third and fourth inter-layer insulators32 and 23. The capacitor hole 96 communicates with the polysilicon plugs12 in the first and second through holes. The tops of the polysiliconplugs 12 are shown through the modified-cylinder-shaped capacitor hole96. The third inter-layer insulator 32 has side portions that are shownthrough the modified-cylinder-shaped capacitor hole 96.

The capacitor hole 96 is formed by a dry etching process using aphoto-resist film. The third inter-layer insulator 32 of silicon nitrideis different or lower in etching rate than the fourth inter-layerinsulator 23 of silicon oxide. Whereas the capacitor hole 96 can beformed by a single known dry etching process, it is not easy to ensurethe in-plane uniformity of the depth of the capacitor hole 96 if usingthe single etching process as well as ensure the depth uniformity overdifferent wafers. It can be preferable, but is not essential, to carryout two dry etching processes in order to form the capacitor hole 96 inthe stack of the third and fourth inter-layer insulators 32 and 23. Forexample, a first dry etching process is carried out to selectively etchthe fourth inter-layer insulator 23, while the third inter-layerinsulator 32 performing as an etching stopper. Then, a second dryetching process is carried out to selectively etch the third inter-layerinsulator 32, while the second inter-layer insulator 22 performing asanother etching stopper. The combination of the first and second dryetching processes can improve the in-plane uniformity of the depth ofthe capacitor hole 96 and the depth uniformity over different wafers.

With reference to FIG. 6, the side portions of the third inter-layerinsulator 32 and the top surfaces of the polysilicon plugs 12 areexposed to an atmosphere in the capacitor hole 96. The side portions ofthe third inter-layer insulator 32 of silicon nitride and the topsurfaces of the polysilicon plugs 12 are then subjected to an oxidationprocess so that the side portions of silicon nitride are modified intosilicon oxynitride films (SiON films) 82, while the polysilicon plugs 12of polysilicon are modified into silicon oxide films 86. Namely, by theoxidation process, the silicon oxynitride films (SiON films) 82 areformed on the side edges of the third inter-layer insulator 32, whilethe silicon oxide films 86 are formed on the top surfaces of thepolysilicon plugs 12.

In some cases, the oxidation process may be realized by a thermaloxidation process that is carried out at 700° C. for 10 minutes, therebyforming the silicon oxynitride film 82 having a thickness ofapproximately 1 nanometer. The thermal oxidation process can be carriedout in either an oxygen atmosphere or a nitrogen atmosphere. When thethermal oxidation process is carried out in the oxygen atmosphere, theside portions of silicon nitride are oxidized by oxygen contained in theoxygen atmosphere. When the thermal oxidation process is carried out inthe nitrogen atmosphere, the side portions of silicon nitride areoxidized by oxygen and/or water that have been eliminated from thesecond and fourth inter-layer insulators 22 and 23 of silicon oxidewhich are exposed to the nitrogen atmosphere in the capacitor hole 96.

In other cases, the oxidation process may also be realized by a plasmaoxidation process, so that the side portions of silicon nitride areoxidized by oxygen that has been eliminated from the second and fourthinter-layer insulators 22 and 23 of silicon oxide which are exposed tothe plasma atmosphere in the capacitor hole 96.

A wet cleaning process is carried out to remove the silicon oxide films86 from the polysilicon plugs 12, while leaving the silicon oxynitridefilms (SiON films) 82 on the side edges of the third inter-layerinsulator 32. The wet cleaning process can be realized by using ahydrogen fluoride solution that is diluted with ammonium water, namelyBHF water, or a hydrogen fluoride solution that is diluted with water,namely DHF water. Use of BHF water or DHF water can remove the siliconoxide films 86 from the polysilicon plugs 12, while leaving the siliconoxynitride films (SiON films) 82 on the side edges of the thirdinter-layer insulator 32.

With reference to FIG. 7, a chemical vapor deposition process is carriedout to form adhesive layers 81 and 81 a of titanium oxide (TiO). Thetitanium oxide adhesive layer 81 is deposited on the surfaces of thesecond and fourth inter-layer insulators 22 and 23 of silicon oxide. Thetitanium oxide adhesive layer 81 a is deposited on the siliconoxynitride films (SiON films) 82 which is adjacent to the side edges ofthe third inter-layer insulator 32. In some cases, the chemical vapordeposition process can be carried out at 650° C. in a titaniumtetrachloride (TiCl₄) gas. The chemical vapor deposition process causesa reaction between titanium of titanium tetrachloride (TiCl₄) andsilicon oxide of the second and fourth inter-layer insulators 22 and 23,thereby forming the titanium oxide adhesive layer 81 on the surfaces ofthe second and fourth inter-layer insulators 22 and 23. The chemicalvapor deposition process also causes another reaction between titaniumof titanium tetrachloride (TiCl₄) and silicon oxynitride of the siliconoxynitride films (SiON films) 82, thereby forming the titanium oxideadhesive layer 81 a on the silicon oxynitride films (SiON films) 82.

The top surfaces of the polysilicon plugs 12 are also exposed to thetitanium tetrachloride (TiCl₄) atmosphere in the capacitor hole 96 sincethe silicon oxide films 86 have been removed by the wet etching process.Thus, the chemical vapor deposition process also causes a silicidationreaction between titanium of titanium tetrachloride (TiCl₄) andpolysilicon of the polysilicon plugs 12, thereby forming titaniumsilicide films 50 on the top surfaces of the polysilicon plugs 12.Namely, the side and bottom walls of the capacitor hole 96 are coveredby the titanium oxide adhesive layers 81 and 81 a and the titaniumsilicide films 50.

The silicon oxynitride films (SiON films) 82 is adjacent to the sideedges of the third inter-layer insulator 32 of silicon nitride. Thetitanium oxide adhesive layer 81 a is also adjacent to the siliconoxynitride films (SiON films) 82. The silicon oxynitride films (SiONfilms) 82 is interposed as an intermediate layer between the thirdinter-layer insulator 32 of silicon nitride (SiN) and the titanium oxide(TiO) adhesive layer 81 a. Silicon oxynitride (SiON) has adhesiveness toboth titanium oxide (TiO) and silicon nitride (SiN). Thus, the siliconoxynitride films (SiON films) 82 have adhesiveness to the siliconnitride (SiN) third inter-layer insulator 32 and also to the titaniumoxide (TiO) adhesive layer 81 a. In other words, the silicon oxynitridefilms (SiON films) 82 provide enhanced adhesiveness between the siliconnitride (SiN) third inter-layer insulator 32 and the titanium oxide(TiO) adhesive layer 81 a.

With reference to FIG. 8, a chemical vapor deposition process is carriedout to form a titanium nitride bottom electrode film 51 on the titaniumoxide (TiO) adhesive layers 81 and 81 a and the titanium silicide films50. The thickness of the titanium nitride bottom electrode film 51 maytypically be, but is not limited to, 10 nanometers. The titanium nitridebottom electrode film 51 is adhered via the titanium oxide (TiO)adhesive layer 81 to the silicon oxide fourth inter-layer insulator 23.Further, the titanium nitride bottom electrode film 51 is adhered viathe titanium oxide (TiO) adhesive layer 81 a and the silicon oxynitridefilms (SiON films) 82 to the silicon nitride (SiN) third inter-layerinsulator 32. In other words, the titanium oxide (TiO) adhesive layer 81provides adhesiveness between the titanium nitride bottom electrode film51 and the silicon oxide fourth inter-layer insulator 23. The titaniumoxide (TiO) adhesive layer 81 a provides adhesiveness between thetitanium nitride bottom electrode film 51 and the silicon oxynitridefilms (SiON films) 82. The silicon oxynitride films (SiON films) 82 alsoprovide enhanced adhesiveness between the titanium oxide (TiO) adhesivelayer 81 a and the silicon nitride (SiN) third inter-layer insulator 32.Thus, the titanium oxide (TiO) adhesive layer 81 a in combination withthe silicon oxynitride films (SiON films) 82 provide enhancedadhesiveness between the titanium nitride bottom electrode film 51 andthe silicon nitride (SiN) third inter-layer insulator 32. The siliconoxynitride films (SiON films) 82 may be regarded as an intermediateadhesive layer, or as an additional adhesive layer in addition to thetitanium oxide (TiO) adhesive layer 81 a.

With reference to FIG. 9, a photo-resist film 71 is selectively formedin the capacitor hole 96. The stack of the titanium nitride bottomelectrode film 51 and the titanium oxide (TiO) adhesive layer 81 has afirst portion which is present in the capacitor hole 96, and a secondportion which is present over the fourth inter-layer insulator 23 ofsilicon oxide. The first portion of the stack of the titanium nitridebottom electrode film 51 and the titanium oxide (TiO) adhesive layer 81is covered by the photo-resist film 71, while the second portion of thestack is not covered by the photo-resist film 71.

With reference to FIG. 10, an etch-back process is carried out to removethe first portion of the stack of the titanium nitride bottom electrodefilm 51 and the titanium oxide (TiO) adhesive layer 81 as well as removean upper portion of the photo-resist film 71 in the capacitor hole 96.Namely, the etch-back process is carried out to leave the second portionof the stack of the titanium nitride bottom electrode film 51 and thetitanium oxide (TiO) adhesive layers 81 and 81 a as well as a lowerportion of the photo-resist film 71 in the capacitor hole 96. As aresult of the etch-back process, the upper surface of the fourthinter-layer insulator 23 is shown, while the side and bottom walls ofthe capacitor hole 96 remain covered by the remaining portion of thestack of the titanium nitride bottom electrode film 51 and the titaniumoxide (TiO) adhesive layers 81 and 81 a.

With reference to FIG. 11, the remaining photo-resist film 71 is removedfrom the capacitor hole 96. In some cases, the removal of the remainingphoto-resist film 71 can be made by using an organic release agent,thereby completing the titanium nitride bottom electrode 51 of themodified-cylinder-shape.

With reference to FIG. 12, an aluminum oxide capacitive insulating film52 is formed on the titanium nitride bottom electrode 51 and on theupper surface of the fourth inter-layer insulator 23 of silicon oxide.The aluminum oxide capacitive insulating film 52 can be formed by usingan atomic layer deposition process. The thickness of the aluminum oxidecapacitive insulating film 52 can typically be, but is not limited to, 6nanometers. A titanium nitride top electrode 53 is formed on thealuminum oxide capacitive insulating film 52. The titanium nitride topelectrode 53 can be formed by using a chemical vapor deposition process.The thickness of the titanium nitride top electrode 53 can typically be,but is not limited to, 15 nanometers.

With reference to FIG. 13, the stack of the aluminum oxide capacitiveinsulating film 52 and the titanium nitride top electrode 53 isselectively removed so as to leave the stack in the capacitor hole 96and over the adjacent portion of the upper surface of the fourthinter-layer insulator 23 of silicon oxide. The adjacent portion of theupper surface is adjacent to the capacitor hole 96. The stack of thealuminum oxide capacitive insulating film 52 and the titanium nitridetop electrode 53 can be selectively removed by a photo-lithographytechnique and a dry etching technique. As a result, the capacitor 54 ofmodified-cylinder-shape is thus formed in the capacitor hole 96 ofmodified-cylinder-shape. The height of the capacitor 54 may typicallybe, but is not limited to, 3 micrometers.

With reference back to FIG. 1, over the memory cell area 100 and theperipheral circuit area 200, a silicon oxide fifth inter-layer insulator24 is formed on the top electrode 53 of the capacitor 54 and on thefourth inter-layer insulator 24. In the peripheral circuit area 200,third and fourth through holes are formed in the stack of the second,third, fourth and fifth inter-layers 22, 32, 23, and 24. The thirdthrough hole communicates with the top of the metal plug 41. The fourththrough hole communicates with the top surface of the first-levelinterconnection 8 a. On the boundary between the memory cell area 100and the peripheral circuit area 200, a fifth through hole is formed inthe fifth inter-layer insulator 24. The fifth through hole communicateswith the top electrode 53 of the capacitor 54.

A titanium nitride film is formed in the third, fourth and fifth throughholes and on the upper surface of the silicon oxide fifth inter-layerinsulator 24. Further, a tungsten film is formed on the titanium nitridefilm so as to fill the third, fourth and fifth through holes. A chemicalmechanical polishing method is carried out to selectively remove thestack of the titanium nitride film and the tungsten film which extendover the upper surface of the silicon oxide fifth inter-layer insulator24, while leaving the stack which fill the third, fourth and fifththrough holes. As a result, first, second, and third metal plugs 42, 43,and 44 are formed in the third, fourth and fifth through holes. Thefirst and second contact plugs 42 and 43 contact with the metal plug 41and the first-level interconnection 8 a. The first contact plug 43 iselectrically connected through the metal plug 41 to the diffusion layer7 of the peripheral circuit transistor. The second contact plug 44 iselectrically connected through the first-level interconnection 8 a andthe metal plug 41 a to the diffusion layer 7 a of the peripheral circuittransistor. The third contact plug 44 contacts with the top electrode 53of the capacitor 54.

A titanium film is deposited by a sputtering process on the uppersurface of the silicon oxide fifth inter-layer insulator 24 and on thetop surfaces of the first, second, and third metal plugs 42, 43, and 44.An aluminum film is deposited by a sputtering process on the titaniumfilm. A titanium nitride film is deposited by a sputtering process onthe aluminum film, thereby forming a stack of the titanium film, thealuminum film, and the titanium nitride film over the silicon oxidefifth inter-layer insulator 24. The stack of the titanium film, thealuminum film, and the titanium nitride film is then patterned by alithography technique and a dry etching technique, thereby formingsecond-level interconnections 61 and 61 a. The second-levelinterconnection 61 contacts with the second and third contact plugs 43and 44. Namely, the second-level interconnection 61 electricallyconnects between the first and third contact plugs 43 and 44. Theadditional second-level interconnection 61 a contacts with the firstcontact plug 42. As a result, the semiconductor memory device of FIG. 1is completed.

(3) Analysis of the Capacitor:

FIG. 14 is a photograph showing a fragmentary cross section of aportion, marked by “k” in FIG. 2, of the capacitor included in thesemiconductor memory device by the above-described series of processesof FIGS. 2-13 in accordance with the first embodiment of the presentinvention. FIG. 14 shows that a silicon oxynitride (SiON) layer isadhered to a silicon nitride (SiN) layer. This demonstrates that thesilicon oxynitride film (SiON film) 82 is adhered to the silicon nitride(SiN) third inter-layer insulator 32. Namely, the silicon oxynitridefilm (SiON film) 82 has an interface to the silicon nitride (SiN) thirdinter-layer insulator 32, wherein the interface is free of any void orpeeling. It is also shown that a titanium oxide (TiO) layer is adheredto the silicon oxynitride (SiON) layer. This demonstrates that thetitanium oxide (TiO) adhesive layer 81 a is adhered to the siliconoxynitride films (SiON films) 82. Namely, the titanium oxide (TiO)adhesive layer 81 a has an interface to the silicon oxynitride film(SiON film) 82, wherein the interface is free of any void or peeling. Itis also shown that a titanium nitride (TiN) layer is adhered to thetitanium oxide (TiO) layer. Thus, the titanium nitride bottom electrodefilm 51 is adhered to the titanium oxide (TiO) adhesive layer 81.Namely, the titanium nitride bottom electrode film 51 has an interfaceto the titanium oxide (TiO) adhesive layer 81, wherein the interface isfree of any void or peeling.

The silicon oxynitride film (SiON film) 82 has adhesiveness to thesilicon nitride (SiN) third inter-layer insulator 32 and also to thetitanium oxide (TiO) adhesive layer 81 a. In other words, the siliconoxynitride films (SiON films) 82 provide enhanced adhesiveness betweenthe silicon nitride (SiN) third inter-layer insulator 32 and thetitanium oxide (TiO) adhesive layer 81 a. The titanium oxide (TiO)adhesive layer 81 a has adhesiveness to the silicon oxynitride films(SiON films) 82 and also to the titanium nitride bottom electrode film51. In other words, the titanium oxide (TiO) adhesive layer 81 a provideenhanced adhesiveness between the silicon oxynitride films (SiON films)82 and the titanium nitride bottom electrode film 51. Thus, the titaniumoxide (TiO) adhesive layer 81 a in combination with the siliconoxynitride films (SiON films) 82 provide enhanced adhesiveness betweenthe titanium nitride bottom electrode film 51 and the silicon nitride(SiN) third inter-layer insulator 32. The silicon oxynitride films (SiONfilms) 82 may be regarded as an intermediate adhesive layer, or as anadditional adhesive layer in addition to the titanium oxide (TiO)adhesive layer 81 a.

FIG. 15 is a photograph showing a fragmentary cross section of a portionof the capacitor in the absence of any adhesive layers between them inaccordance with a comparative example to the first embodiment of thepresent invention. FIG. 15 shows that a titanium nitride (TiN) layer isadjacent to a silicon nitride (SiN) layer in the absence of any adhesivelayers between them. The titanium nitride (TiN) layer has an interfaceto a silicon nitride (SiN) layer, wherein the interface includes voids.This demonstrates that the titanium nitride bottom electrode film 51 isincompletely adhered to the silicon nitride (SiN) third inter-layerinsulator 32. The titanium nitride bottom electrode film 51 has aninterface to the silicon nitride (SiN) third inter-layer insulator 32,wherein the interface has voids. This demonstrates that the adhesivenessbetween the titanium nitride bottom electrode film 51 and the siliconnitride (SiN) third inter-layer insulator 32 is so weak as to providepoor thermal stress stability to the interface between the titaniumnitride bottom electrode film 51 and the silicon nitride (SiN) thirdinter-layer insulator 32. In other words, voids may be formed at theinterface between the titanium nitride bottom electrode film 51 and thesilicon nitride (SiN) third inter-layer insulator 32 during the thermalprocess for forming the capacitor.

FIG. 16A is a diagram showing measured time zero dielectric breakdowncharacteristics of the capacitors of the first embodiment of the presentinvention and the comparative example. 10 k-bits array test elementgroups of the capacitors were used to measure time zero dielectricbreakdown characteristic of the capacitor. The bottom electrode is fixedat 0V, while the top electrode is applied with a variable voltage thatis swept from 0V to −10V. In FIG. 16A, the vertical axis represents thecumulative probability (%), while the horizontal axis represents theabsolute value of the breakdown voltage. ◯ represents distributions ofmeasured breakdown voltages of the capacitors of the first embodiment ofthe present invention.  represents distributions of measured breakdownvoltages of the capacitors of the comparative example. The breakdownvoltages of the capacitors are measured at 90° C.

Some of the capacitors of the comparative example have smaller absolutevalues of the breakdown voltages than 6V. Such capacitors with smallerabsolute values of the breakdown voltages than 6V may be regarded asdefective capacitors. In contrast, all of the capacitors of the firstembodiment of the present invention have larger absolute values of thebreakdown voltages than 6V. All of the capacitors of the firstembodiment of the present invention may be regarded as non-defectivecapacitors.

With reference back to FIG. 15, the capacitor of the comparative examplehas the void-containing interface between the titanium nitride bottomelectrode 51 and the silicon nitride inter-layer insulator 32. Withreference further back to FIG. 14, the capacitor of the first embodimentof the present invention has a void-free interface between the titaniumnitride bottom electrode 51 and the silicon nitride inter-layerinsulator 32. The capacitor of the comparative example having thevoid-containing interface between the titanium nitride bottom electrode51 and the silicon nitride inter-layer insulator 32 have poor time zerodielectric breakdown characteristics. The capacitor of the firstembodiment of the present invention having the void-free interfacebetween the titanium nitride bottom electrode 51 and the silicon nitrideinter-layer insulator 32 have desired time zero dielectric breakdowncharacteristics.

FIG. 16B is a diagram showing measured time zero dielectric breakdowncharacteristics of the capacitors of the first embodiment of the presentinvention and the comparative example. 10 k-bits array test elementgroups of the capacitors were used to measure time zero dielectricbreakdown characteristic of the capacitor. The bottom electrode is fixedat 0V, while the top electrode is applied with a variable voltage thatis swept from 0V to 10V In FIG. 16B, the vertical axis represents thecumulative probability (%), while the horizontal axis represents theabsolute value of the breakdown voltage. ◯ represents distributions ofmeasured breakdown voltages of the capacitors of the first embodiment ofthe present invention.  represents distributions of measured breakdownvoltages of the capacitors of the comparative example. The breakdownvoltages of the capacitors are measured at 90° C.

Some of the capacitors of the comparative example have smaller absolutevalues of the breakdown voltages than 4.5V. Such capacitors with smallerabsolute values of the breakdown voltages than 4.5V may be regarded asdefective capacitors. In contrast, all of the capacitors of the firstembodiment of the present invention have larger absolute values of thebreakdown voltages than 5.5V. All of the capacitors of the firstembodiment of the present invention may be regarded as non-defectivecapacitors.

With reference back to FIG. 15, the capacitor of the comparative examplehas the void-containing interface between the titanium nitride bottomelectrode 51 and the silicon nitride inter-layer insulator 32. Withreference further back to FIG. 14, the capacitor of the first embodimentof the present invention has a void-free interface between the titaniumnitride bottom electrode 51 and the silicon nitride inter-layerinsulator 32. The capacitor of the comparative example having thevoid-containing interface between the titanium nitride bottom electrode51 and the silicon nitride inter-layer insulator 32 have poor time zerodielectric breakdown characteristics. The capacitor of the firstembodiment of the present invention having the void-free interfacebetween the titanium nitride bottom electrode 51 and the silicon nitrideinter-layer insulator 32 have desired time zero dielectric breakdowncharacteristics.

Capacitors of advanced DRAMs are likely to have high aspect ratio of theheight to the horizontal dimension due to high density integration andscaling down of the capacitors. This means that the capacitor hole 96has to have high aspect ratio of the depth to the horizontal dimension.

The silicon nitride third inter-layer insulator 32 performs not only asthe inter-layer insulator but also as the etching stopper in the etchingprocess for etching the silicon oxide fourth inter-layer insulator 23.The depth of the capacitor hole 96 is defined by the thickness of thesilicon oxide fourth inter-layer insulator 23. If the depth of thecapacitor hole 96 is deep, this means that the thickness of the siliconoxide fourth inter-layer insulator 23 is thick. If the thickness of thesilicon oxide fourth inter-layer insulator 23 is increased, then thethickness of the silicon nitride third inter-layer insulator 32 needs tobe also increased. Namely, if the depth of the capacitor hole 96 isincreased, then this needs that the thickness of the silicon nitridethird inter-layer insulator 32 is increased. As demonstrated above, thetitanium nitride bottom electrode film 51 has weak adhesiveness to thesilicon nitride third inter-layer insulator 32. The increase in thethickness of the silicon nitride third inter-layer insulator 32 weakensadhesiveness between the titanium nitride bottom electrode film 51 andthe silicon nitride third inter-layer insulator 32. The titanium oxide(TiO) adhesive layer 81 a in combination with the silicon oxynitridefilms (SiON films) 82 provide enhanced adhesiveness between the titaniumnitride bottom electrode film 51 and the silicon nitride (SiN) thirdinter-layer insulator 32.

(4) Modifications:

In accordance with the first embodiment of the present invention, thecapacitive insulating film 52 of the capacitor 54 is realized by thealuminum oxide film. It is possible as modifications that the capacitiveinsulating film 52 of the capacitor 54 can be realized by a hafniumoxide film, a tantalum oxide film, or a zirconium oxide film, or a stackof those films.

In accordance with the first embodiment of the present invention, thepolysilicon plugs 12 provide electrical connections between the bottomelectrode 51 of the capacitor 54 and the polysilicon plugs 11 which areconnected to the diffusion layers 5 of the memory cell switchingtransistors. The plugs 12 providing electrical connections between thebottom electrode 51 and the polysilicon plugs 11 can also be realized byother metal plugs, for example, a titanium nitride film or a stack of atitanium nitride film and a tungsten film.

In accordance with the first embodiment of the present invention, thebottom electrode 51 is realized by a titanium nitride film. The bottomelectrode 51 can also be realized by other conductive materials.

In accordance with the first embodiment of the present invention, theadhesive layers 81 and 81 a are realized by a titanium oxide (TiO) film,and the intermediate adhesive layer 82 is realized by a siliconoxynitride (SiON) film. The side portions of the third inter-layerinsulator 32 of silicon nitride are subjected to an oxidation process sothat the side portions of silicon nitride are modified into siliconoxynitride films (SiON films) 82. The adhesive layers 81 and 81 a andthe intermediate adhesive layer 82 can also be realized by othermaterials which provide adhesiveness between the bottom electrode 51 andthe third inter-layer insulator 32.

Second Embodiment

The second embodiment provides a semiconductor memory device including ametal-insulator-metal capacitor and a method of forming the same. Thedescriptions of the second embodiment will be made with reference toFIGS. 17-22.

(1) Semiconductor Memory Device and Capacitor Structure:

FIG. 17 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a second preferredembodiment of the present invention. FIG. 18 is a fragmentary enlargedcross sectional view illustrating a capacitor structure included in amemory cell in the semiconductor device of FIG. 17.

Similarly to the first embodiment, the semiconductor memory device ofthe second embodiment includes the memory cell area 100 and theperipheral circuit area 200, which are adjacent to each other. Thememory cell area 100 has the memory cell which includes the memory celltransistors and the capacitor 54. The peripheral circuit area 200 hasthe peripheral circuit.

The following descriptions will focus on the differences of the secondembodiment from the first embodiment.

In accordance with the first embodiment of the present invention, thethird inter-layer insulator 32 of silicon nitride is provided over thesecond inter-layer insulator 22 of silicon oxide and the fourthinter-layer insulator 23 of silicon oxide. The capacitor hole 96 isformed in the stack of the fourth inter-layer insulator 23 of siliconoxide and the silicon nitride third inter-layer insulator 32. Thesilicon nitride third inter-layer insulator 32 performs as the etchingstopper in the etching process for forming the capacitor hole 96. Thesilicon oxynitride film 82 and the titanium oxide adhesive layer 81 aare interposed between the titanium nitride bottom electrode film 51 andthe silicon nitride third inter-layer insulator 32. The siliconoxynitride film 82 in combination with the titanium oxide adhesive layer81 a provide enhanced adhesiveness between the titanium nitride bottomelectrode film 51 and the silicon nitride third inter-layer insulator32.

In accordance with the second embodiment of the present invention, athird inter-layer insulator 32 a of silicon oxynitride film is providedover the second inter-layer insulator 22 of silicon oxide and the fourthinter-layer insulator 23 of silicon oxide. The capacitor hole 96 isformed in the stack of the fourth inter-layer insulator 23 of siliconoxide and the silicon oxynitride third inter-layer insulator 32 a. Thesilicon oxynitride third inter-layer insulator 32 a performs as anetching stopper in the etching process for forming the capacitor hole96. The titanium oxide adhesive layer 81 a is interposed between thetitanium nitride bottom electrode film 51 and the silicon nitride thirdinter-layer insulator 32. The silicon oxynitride film 82 of the firstembodiment is absent in the second embodiment. Titanium oxide (TiO) hasadhesiveness to silicon oxynitride (SiON) and also to titanium nitride(TiN). In other words, the titanium oxide adhesive layer 81 a hasadhesiveness to the titanium nitride bottom electrode film 51 and alsoto the silicon nitride third inter-layer insulator 32. Thus, thetitanium oxide adhesive layer 81 a provide enhanced adhesiveness betweenthe titanium nitride bottom electrode film 51 and the silicon nitridethird inter-layer insulator 32. There is no process for forming thesilicon oxynitride film 82.

(2) Method of Forming Semiconductor Memory Device and Capacitor:

A method of forming the semiconductor memory device of FIG. 17 includingthe memory cell capacitor of FIG. 18 will be described. FIGS. 19 through22 are fragmentary cross sectional elevation views illustratingsemiconductor memory devices in sequential steps involved in a method offorming the semiconductor memory device of FIGS. 17 and 18 in accordancewith the second embodiment of the present invention.

With reference back to FIG. 3, a silicon substrate 10 with a main faceis prepared. An isolating film 2 such as a local oxidation of siliconfilm is formed on the main face of the silicon substrate 10 so that theisolating film 2 defines first and second active regions of the siliconsubstrate 10 in the memory cell area 100 and the peripheral circuit area200 shown in FIG. 1. The first and second active regions are surroundedby the isolating film 2. First and second gate structures are formed onthe first active region, while a third gate structure is formed on thesecond active region. Each of the gate structure includes a gateinsulating film 3, a gate electrode 4, and an insulating film 31. Theprocesses for forming the first to third gate structures may be theknown processes. Diffusion layers 5 and 6 that perform as source anddrain regions are formed in the first active region, while diffusionlayers 7 and 7 a that perform as source and drain regions are formed inthe second active region. The processes for forming the diffusion layers5, 6, 7 and 7 a may be the known processes. As a result, a pair ofmemory cell transistors is formed in the first active region, while aperipheral circuit transistor is formed in the second active region.

A first inter-layer insulator 21 is formed over the memory cell area 100and the peripheral circuit area 200. Namely, the first inter-layerinsulator 21 is formed over the first and second active regions and theisolation film 2. The first inter-layer insulator 21 embeds the memorycell transistors and the peripheral circuit transistor.

In the memory cell area 100, first to third contact holes are formed inthe first inter-layer insulator 21, so that the first contact holecommunicates with the diffusion layer 6, and the second and thirdcontact holes communicate with the diffusion layers 5. In the peripheralcircuit area 200, fourth and fifth contact holes are formed in the firstinter-layer insulator 21, so that the fourth and fifth contact holescommunicate with the diffusion layers 7 and 7 a. Deposition of apolysilicon film and subsequent etch-back process is carried out. Apolysilicon plug 11 a is formed in the first contact hole, whilepolysilicon plugs 11 are formed in the second and third contact holes.The polysilicon plug 11 a contacts with the diffusion layer 6. Thepolysilicon plugs 11 contact with the diffusion layers 5. Further,deposition of a metal film and subsequent etch-back process is carriedout. Metal plugs 41 and 41 a are formed in the fourth and fifth contactholes. The metal plugs 41 and 41 a contact with the diffusion layers 7and 7 a.

A bit-line 8 and a first-level interconnection 8 a are formed on thefirst inter-layer insulator 21 so that the bit-line 8 contacts with thetop of the polysilicon plug 11 a and the first-level interconnection 8 acontacts with the metal plug 41 a. The bit-line 8 is electricallyconnected through the polysilicon plug 11 a to the diffusion layer 6.The first-level interconnection 8 a is electrically connected throughthe metal plug 41 a to the diffusion layer 7 a. The bit-line 8 and thefirst-level interconnection 8 a may be realized by a tungsten film.

Over the memory cell area 100 and the peripheral circuit area 200, asecond inter-layer insulator 22 is formed over the first inter-layerinsulator 21, the polysilicon plugs 11 and 11 a, and the metal plugs 41and 41 a, as well as over the bit line 8 and the first-levelinterconnection 8 a. The second inter-layer insulator 22 embeds the bitline 8 and the first-level interconnection 8 a. The second inter-layerinsulator 22 can be realized by a silicon oxide film.

In the memory cell area 100, first and second through holes are formedin the second inter-layer insulator 22 so that the first and secondthrough holes communicate with the polysilicon plugs 11. Deposition of apolysilicon film and subsequent etch-back process is carried out so thatpolysilicon plugs 12 are formed in the first and second through holes ofthe second inter-layer insulator 22. The polysilicon plugs 12 contactwith the polysilicon plugs 11 which further contact with the diffusionlayers 5. Thus, the polysilicon plugs 12 are eclectically connectedthrough the polysilicon plugs 11 to the diffusion layers 5 of the memorycell transistors.

With reference to FIG. 19, over the memory cell area 100 and theperipheral circuit area 200, a third inter-layer insulator 32 a isformed on the second inter-layer insulator 22 and on the titaniumsilicide films 50. The third inter-layer insulator 32 a can be realizedby a silicon oxynitride film. The silicon oxynitride third inter-layerinsulator 32 a can be formed at 400° C. under 400 Pa by using, as sourcegases, a monosilane gas (SiH₄), an ammonium gas (NH₃), a dinitrogenmonoxide gas (N₂O), and a nitrogen gas (N₂). Further, a fourthinter-layer insulator 23 is formed on the third inter-layer insulator32. The fourth inter-layer insulator 23 can be realized by a siliconoxide film. The thickness of the fourth inter-layer insulator 23 maytypically be, but is not limited to, 3 micrometers.

With reference to FIG. 20, in the memory cell area 100, a capacitor hole96 is formed in the stack of the third and fourth inter-layer insulators32 a and 23. The capacitor hole 96 may be modified-cylinder-shaped. Inplan view, the capacitor hole 96 has a torus shape. The capacitor hole96 penetrates the stack of the third and fourth inter-layer insulators32 a and 23. The capacitor hole 96 communicates with the polysiliconplugs 12 in the first and second through holes. The tops of thepolysilicon plugs 12 are shown through the modified-cylinder-shapedcapacitor hole 96. The third inter-layer insulator 32 a has sideportions that are shown through the modified-cylinder-shaped capacitorhole 96.

The capacitor hole 96 is formed by a dry etching process using aphoto-resist film. The third inter-layer insulator 32 a of siliconoxynitride is different or lower in etching rate than the fourthinter-layer insulator 23 of silicon oxide. Whereas the capacitor hole 96can be formed by a single known dry etching process, it is not easy toensure the in-plane uniformity of the depth of the capacitor hole 96 ifusing the single etching process as well as ensure the depth uniformityover different wafers. It can be preferable, but is not essential, tocarry out two dry etching processes in order to form the capacitor hole96 in the stack of the third and fourth inter-layer insulators 32 a and23. For example, a first dry etching process is carried out toselectively etch the fourth inter-layer insulator 23, while the thirdinter-layer insulator 32 a performing as an etching stopper. Then, asecond dry etching process is carried out to selectively etch the thirdinter-layer insulator 32 a, while the second inter-layer insulator 22performing as another etching stopper. The combination of the first andsecond dry etching processes can improve the in-plane uniformity of thedepth of the capacitor hole 96 and the depth uniformity over differentwafers.

With reference to FIG. 21, the side portions of the third inter-layerinsulator 32 and the top surfaces of the polysilicon plugs 12 areexposed to an atmosphere in the capacitor hole 96. A chemical vapordeposition process is carried out to form adhesive layers 81 and 81 a oftitanium oxide (TiO). The titanium oxide adhesive layer 81 is depositedon the surfaces of the second and fourth inter-layer insulators 22 and23 of silicon oxide. The titanium oxide adhesive layer 81 a is depositedon the silicon oxynitride third inter-layer insulator (SiON) 32. In somecases, the chemical vapor deposition process can be carried out at 650°C. in a titanium tetrachloride (TiCl₄) gas. The chemical vapordeposition process causes a reaction between titanium of titaniumtetrachloride (TiCl₄) and silicon oxide of the second and fourthinter-layer insulators 22 and 23, thereby forming the titanium oxideadhesive layer 81 on the surfaces of the second and fourth inter-layerinsulators 22 and 23. The chemical vapor deposition process also causesanother reaction between titanium of titanium tetrachloride (TiCl₄) andsilicon oxynitride of the silicon oxynitride third inter-layer insulator(SiON) 32, thereby forming the titanium oxide adhesive layer 81 a on thesilicon oxynitride third inter-layer insulator (SiON) 32.

The top surfaces of the polysilicon plugs 12 are also exposed to thetitanium tetrachloride (TiCl₄) atmosphere in the capacitor hole 96.Thus, the chemical vapor deposition process also causes a silicidationreaction between titanium of titanium tetrachloride (TiCl₄) andpolysilicon of the polysilicon plugs 12, thereby forming titaniumsilicide films 50 on the top surfaces of the polysilicon plugs 12.Namely, the side and bottom walls of the capacitor hole 96 are coveredby the titanium oxide adhesive layers 81 and 81 a and the titaniumsilicide films 50.

The titanium oxide adhesive layer 81 a is adjacent to the siliconoxynitride third inter-layer insulator (SiON) 32 a. Silicon oxynitride(SiON) has adhesiveness to titanium oxide (TiO). Thus, the titaniumoxide (TiO) adhesive layer 81 a has adhesiveness to the siliconoxynitride third inter-layer insulator (SiON) 32 a.

With reference to FIG. 22, a chemical vapor deposition process iscarried out to form a titanium nitride bottom electrode film 51 on thetitanium oxide (TiO) adhesive layers 81 and 81 a and the titaniumsilicide films 50. The thickness of the titanium nitride bottomelectrode film 51 may typically be, but is not limited to, 10nanometers. The titanium nitride bottom electrode film 51 is adhered viathe titanium oxide (TiO) adhesive layer 81 to the silicon oxide fourthinter-layer insulator 23. Further, the titanium nitride bottom electrodefilm 51 is adhered via the titanium oxide (TiO) adhesive layer 81 a tothe silicon oxynitride third inter-layer insulator (SiON) 32 a. In otherwords, the titanium oxide (TiO) adhesive layer 81 provides adhesivenessbetween the titanium nitride bottom electrode film 51 and the siliconoxide fourth inter-layer insulator 23. The titanium oxide (TiO) adhesivelayer 81 a provides adhesiveness between the titanium nitride bottomelectrode film 51 and the silicon oxynitride third inter-layer insulator(SiON) 32 a. Thus, the titanium oxide (TiO) adhesive layer 81 a providesenhanced adhesiveness between the titanium nitride bottom electrode film51 and the silicon oxynitride third inter-layer insulator (SiON) 32 a.

A photo-resist film is selectively formed in the capacitor hole 96. Thestack of the titanium nitride bottom electrode film 51 and the titaniumoxide (TiO) adhesive layer 81 has a first portion which is present inthe capacitor hole 96, and a second portion which is present over thefourth inter-layer insulator 23 of silicon oxide. The first portion ofthe stack of the titanium nitride bottom electrode film 51 and thetitanium oxide (TiO) adhesive layer 81 is covered by the photo-resistfilm, while the second portion of the stack is not covered by thephoto-resist film.

An etch-back process is carried out to remove the first portion of thestack of the titanium nitride bottom electrode film 51 and the titaniumoxide (TiO) adhesive layer 81 as well as remove an upper portion of thephoto-resist film in the capacitor hole 96. Namely, the etch-backprocess is carried out to leave the second portion of the stack of thetitanium nitride bottom electrode film 51 and the titanium oxide (TiO)adhesive layers 81 and 81 a as well as a lower portion of thephoto-resist film in the capacitor hole 96. As a result of the etch-backprocess, the upper surface of the fourth inter-layer insulator 23 isshown, while the side and bottom walls of the capacitor hole 96 remaincovered by the remaining portion of the stack of the titanium nitridebottom electrode film 51 and the titanium oxide (TiO) adhesive layers 81and 81 a.

The remaining photo-resist film is removed from the capacitor hole 96.In some cases, the removal of the remaining photo-resist film can bemade by using an organic release agent, thereby completing the titaniumnitride bottom electrode 51 of the modified-cylinder-shape.

With reference back to FIG. 17, an aluminum oxide capacitive insulatingfilm 52 is formed on the titanium nitride bottom electrode 51 and on theupper surface of the fourth inter-layer insulator 23 of silicon oxide.The aluminum oxide capacitive insulating film 52 can be formed by usingan atomic layer deposition process. The thickness of the aluminum oxidecapacitive insulating film 52 can typically be, but is not limited to, 6nanometers. A titanium nitride top electrode 53 is formed on thealuminum oxide capacitive insulating film 52. The titanium nitride topelectrode 53 can be formed by using a chemical vapor deposition process.The thickness of the titanium nitride top electrode 53 can typically be,but is not limited to, 15 nanometers.

The stack of the aluminum oxide capacitive insulating film 52 and thetitanium nitride top electrode 53 is selectively removed so as to leavethe stack in the capacitor hole 96 and over the adjacent portion of theupper surface of the fourth inter-layer insulator 23 of silicon oxide.The adjacent portion of the upper surface is adjacent to the capacitorhole 96. The stack of the aluminum oxide capacitive insulating film 52and the titanium nitride top electrode 53 can be selectively removed bya photo-lithography technique and a dry etching technique. As a result,the capacitor 54 of modified-cylinder-shape is thus formed in thecapacitor hole 96 of modified-cylinder-shape. The height of thecapacitor 54 may typically be, but is not limited to, 3 micrometers.

Over the memory cell area 100 and the peripheral circuit area 200, asilicon oxide fifth inter-layer insulator 24 is formed on the topelectrode 53 of the capacitor 54 and on the fourth inter-layer insulator24. In the peripheral circuit area 200, third and fourth through holesare formed in the stack of the second, third, fourth and fifthinter-layers 22, 32, 23, and 24. The third through hole communicateswith the top of the metal plug 41. The fourth through hole communicateswith the top surface of the first-level interconnection 8 a. On theboundary between the memory cell area 100 and the peripheral circuitarea 200, a fifth through hole is formed in the fifth inter-layerinsulator 24. The fifth through hole communicates with the top electrode53 of the capacitor 54.

A titanium nitride film is formed in the third, fourth and fifth throughholes and on the upper surface of the silicon oxide fifth inter-layerinsulator 24. Further, a tungsten film is formed on the titanium nitridefilm so as to fill the third, fourth and fifth through holes. A chemicalmechanical polishing method is carried out to selectively remove thestack of the titanium nitride film and the tungsten film which extendover the upper surface of the silicon oxide fifth inter-layer insulator24, while leaving the stack which fill the third, fourth and fifththrough holes. As a result, first, second, and third metal plugs 42, 43,and 44 are formed in the third, fourth and fifth through holes. Thefirst and second contact plugs 42 and 43 contact with the metal plug 41and the first-level interconnection 8 a. The first contact plug 43 iselectrically connected through the metal plug 41 to the diffusion layer7 of the peripheral circuit transistor. The second contact plug 44 iselectrically connected through the first-level interconnection 8 a andthe metal plug 41 a to the diffusion layer 7 a of the peripheral circuittransistor. The third contact plug 44 contacts with the top electrode 53of the capacitor 54.

A titanium film is deposited by a sputtering process on the uppersurface of the silicon oxide fifth inter-layer insulator 24 and on thetop surfaces of the first, second, and third metal plugs 42, 43, and 44.An aluminum film is deposited by a sputtering process on the titaniumfilm. A titanium nitride film is deposited by a sputtering process onthe aluminum film, thereby forming a stack of the titanium film, thealuminum film, and the titanium nitride film over the silicon oxidefifth inter-layer insulator 24. The stack of the titanium film, thealuminum film, and the titanium nitride film is then patterned by alithography technique and a dry etching technique, thereby formingsecond-level interconnections 61 and 61 a. The second-levelinterconnection 61 contacts with the second and third contact plugs 43and 44. Namely, the second-level interconnection 61 electricallyconnects between the first and third contact plugs 43 and 44. Theadditional second-level interconnection 61 a contacts with the firstcontact plug 42. As a result, the semiconductor memory device of FIG. 17is completed.

In accordance with the second embodiment, there is carried out nooxidation process for oxidizing the side edge of the third inter-layerinsulator 32 a. There is no need to form the silicon oxynitride film(SiON film) 82 which is formed in the first embodiment. In the firstembodiment, the titanium oxide (TiO) adhesive layer 81 a in combinationwith the silicon oxynitride films (SiON films) 82 provide adhesivenessbetween the bottom electrode layer 51 and the third inter-layerinsulator 32. In the second embodiment, the titanium oxide (TiO)adhesive layer 81 a provides adhesiveness between the bottom electrodelayer 51 and the third inter-layer insulator 32.

Third Embodiment

The third embodiment provides a semiconductor memory device including ametal-insulator-metal capacitor including a pedestal bottom electrodeand a method of forming the same. The descriptions of the thirdembodiment will be made with reference to FIGS. 23-29.

(1) Semiconductor Memory Device and Capacitor Structure:

FIG. 23 is a fragmentary cross sectional elevation view illustrating asemiconductor memory device in accordance with a third preferredembodiment of the present invention. FIG. 24 is a fragmentary enlargedcross sectional view illustrating a capacitor structure with a pedestalbottom electrode which is included in a memory cell in the semiconductordevice of FIG. 23.

Similarly to the first embodiment, the semiconductor memory device ofthe second embodiment includes the memory cell area 100 and theperipheral circuit area 200, which are adjacent to each other. Thememory cell area 100 has the memory cell which includes the memory celltransistors and the capacitor 54. The peripheral circuit area 200 hasthe peripheral circuit.

The following descriptions will focus on the differences of the thirdembodiment from the first embodiment.

In accordance with the first embodiment of the present invention, thecapacitor 54 has a three-layered structure which extends along thebottom and side walls of the capacitor hole 96, while the capacitor hole96 is filled with the capacitor 54 and the fifth inter-layer insulator24. The three layered structure includes the bottom electrode film 51,the capacitive insulating film 52, and the top layer 53.

In accordance with the third embodiment of the present invention, thecapacitor 54 is disposed over the second inter-layer insulator 22. Thecapacitor 54 is disposed in a capacitor hole which is formed in thefourth inter-layer insulator 23. The capacitor hole has a cylindricalshape. The capacitor 54 includes a pedestal bottom electrode 51, acapacitive insulating film 52 and a top electrode film 53. The pedestalbottom electrode 51 may be modified-cylinder-shaped. In plan view, thepedestal bottom electrode 51 has a torus shape. The pedestal bottomelectrode 51 is disposed over the titanium silicide films 50 and theadhesive layers 81. The titanium silicide films 50 are disposed on thetops of the polysilicon plugs 12. The adhesive layers 81 are disposed onadjacent portions of the top surface of the second inter-layer insulator22, wherein the adjacent portions are adjacent to the top surface of thesecond inter-layer insulator 22. The pedestal bottom electrode 51 ofmodified-cylinder-shape is spatially separated by a cylinder-shaped gapfrom the side walls of the capacitor hole. The pedestal bottom electrode51 of modified-cylinder-shape also has a cylinder-shaped center hollow.

Titanium oxide (TiO) adhesive layers 81 and 81 a in combination withsilicon oxynitride films 82 are interposed between the pedestal bottomelectrode film 51 and the silicon nitride third inter-layer insulator32. The titanium oxide (TiO) adhesive layers 81 and 81 a in combinationwith the silicon oxynitride films 82 provide enhanced adhesivenessbetween the pedestal bottom electrode film 51 and the silicon nitridethird inter-layer insulator 32.

The capacitive insulating film 52 is disposed on the surface of thepedestal bottom electrode 51 as well as on the bottom and side walls ofthe capacitor hole and over adjacent portions of the top surface of thefourth inter-layer insulator 23. The bottom wall of the capacitor holeis constituted by the silicon nitride third inter-layer insulator 32 andthe silicon oxynitride films 82. The side wall of the capacitor hole isconstituted by the side wall of the fourth inter-layer insulator 23. Thecapacitive insulating film 52 is thus present in the cylinder-shaped gapand also in the cylinder-shaped center hollow.

The top electrode film 53 is disposed on the capacitive insulating film52 to form a stack of the capacitive insulating film 52 and the topelectrode film 53. The stack of the capacitive insulating film 52 andthe top electrode film 53 fill the cylinder-shaped gap and also in thecylinder-shaped center hollow.

(2) Method of Forming Semiconductor Memory Device and Capacitor:

A method of forming the semiconductor memory device of FIG. 23 includingthe memory cell capacitor of FIG. 24 will be described. FIGS. 25 through29 are fragmentary cross sectional elevation views illustratingsemiconductor memory devices in sequential steps involved in a method offorming the semiconductor memory device of FIGS. 23 and 24 in accordancewith the third embodiment of the present invention.

With reference to FIG. 25, a silicon substrate 10 with a main face isprepared. An isolating film 2 such as a local oxidation of silicon filmis formed on the main face of the silicon substrate 10 so that theisolating film 2 defines first and second active regions of the siliconsubstrate 10 in the memory cell area 100 and the peripheral circuit area200 shown in FIG. 23. The first and second active regions are surroundedby the isolating film 2. First and second gate structures are formed onthe first active region, while a third gate structure is formed on thesecond active region. Each of the gate structure includes a gateinsulating film 3, a gate electrode 4, and an insulating film 31. Theprocesses for forming the first to third gate structures may be theknown processes. Diffusion layers 5 and 6 that perform as source anddrain regions are formed in the first active region, while diffusionlayers 7 and 7 a that perform as source and drain regions are formed inthe second active region. The processes for forming the diffusion layers5, 6, 7 and 7 a may be the known processes. As a result, a pair ofmemory cell transistors is formed in the first active region, while aperipheral circuit transistor is formed in the second active region.

A first inter-layer insulator 21 is formed over the memory cell area 100and the peripheral circuit area 200. Namely, the first inter-layerinsulator 21 is formed over the first and second active regions and theisolation film 2. The first inter-layer insulator 21 embeds the memorycell transistors and the peripheral circuit transistor.

In the memory cell area 100, first to third contact holes are formed inthe first inter-layer insulator 21, so that the first contact holecommunicates with the diffusion layer 6, and the second and thirdcontact holes communicate with the diffusion layers 5. In the peripheralcircuit area 200, fourth and fifth contact holes are formed in the firstinter-layer insulator 21, so that the fourth and fifth contact holescommunicate with the diffusion layers 7 and 7 a. Deposition of apolysilicon film and subsequent etch-back process is carried out. Apolysilicon plug 11 a is formed in the first contact hole, whilepolysilicon plugs 11 are formed in the second and third contact holes.The polysilicon plug 11 a contacts with the diffusion layer 6. Thepolysilicon plugs 11 contact with the diffusion layers 5. Further,deposition of a metal film and subsequent etch-back process is carriedout. Metal plugs 41 and 41 a are formed in the fourth and fifth contactholes. The metal plugs 41 and 41 a contact with the diffusion layers 7and 7 a.

A bit-line 8 and a first-level interconnection 8 a are formed on thefirst inter-layer insulator 21 so that the bit-line 8 contacts with thetop of the polysilicon plug 11 a and the first-level interconnection 8 acontacts with the metal plug 41 a. The bit-line 8 is electricallyconnected through the polysilicon plug 11 a to the diffusion layer 6.The first-level interconnection 8 a is electrically connected throughthe metal plug 41 a to the diffusion layer 7 a. The bit-line 8 and thefirst-level interconnection 8 a may be realized by a tungsten film.

Over the memory cell area 100 and the peripheral circuit area 200, asecond inter-layer insulator 22 is formed over the first inter-layerinsulator 21, the polysilicon plugs 11 and 11 a, and the metal plugs 41and 41 a, as well as over the bit line 8 and the first-levelinterconnection 8 a. The second inter-layer insulator 22 embeds the bitline 8 and the first-level interconnection 8 a. The second inter-layerinsulator 22 can be realized by a silicon oxide film.

In the memory cell area 100, first and second through holes are formedin the second inter-layer insulator 22 so that the first and secondthrough holes communicate with the polysilicon plugs 11. Deposition of apolysilicon film and subsequent etch-back process is carried out so thatpolysilicon plugs 12 are formed in the first and second through holes ofthe second inter-layer insulator 22. The polysilicon plugs 12 contactwith the polysilicon plugs 11 which further contact with the diffusionlayers 5. Thus, the polysilicon plugs 12 are eclectically connectedthrough the polysilicon plugs 11 to the diffusion layers 5 of the memorycell transistors.

Over the memory cell area 100 and the peripheral circuit area 200, athird inter-layer insulator 32 is formed on the second inter-layerinsulator 22 and on the titanium silicide films 50. The thirdinter-layer insulator 32 can be realized by a silicon nitride film.Further, a fourth inter-layer insulator 23 is formed on the thirdinter-layer insulator 32. The fourth inter-layer insulator 23 can berealized by a silicon oxide film. The thickness of the fourthinter-layer insulator 23 may typically be, but is not limited to, 3micrometers.

In the memory cell area 100, a capacitor hole 96 is formed in the stackof the third and fourth inter-layer insulators 32 and 23. The capacitorhole 96 may be modified-cylinder-shaped. In plan view, the capacitorhole 96 has a torus shape. The capacitor hole 96 penetrates the stack ofthe third and fourth inter-layer insulators 32 and 23. The capacitorhole 96 communicates with the polysilicon plugs 12 in the first andsecond through holes. The tops of the polysilicon plugs 12 are shownthrough the modified-cylinder-shaped capacitor hole 96. The thirdinter-layer insulator 32 has side portions that are shown through themodified-cylinder-shaped capacitor hole 96.

The capacitor hole 96 is formed by a dry etching process using aphoto-resist film. The third inter-layer insulator 32 of silicon nitrideis different or lower in etching rate than the fourth inter-layerinsulator 23 of silicon oxide. Whereas the capacitor hole 96 can beformed by a single known dry etching process, it is not easy to ensurethe in-plane uniformity of the depth of the capacitor hole 96 if usingthe single etching process as well as ensure the depth uniformity overdifferent wafers. It can be preferable, but is not essential, to carryout two dry etching processes in order to form the capacitor hole 96 inthe stack of the third and fourth inter-layer insulators 32 and 23. Forexample, a first dry etching process is carried out to selectively etchthe fourth inter-layer insulator 23, while the third inter-layerinsulator 32 performing as an etching stopper. Then, a second dryetching process is carried out to selectively etch the third inter-layerinsulator 32, while the second inter-layer insulator 22 performing asanother etching stopper. The combination of the first and second dryetching processes can improve the in-plane uniformity of the depth ofthe capacitor hole 96 and the depth uniformity over different wafers.

With reference to FIG. 26, the side portions of the third inter-layerinsulator 32 and the top surfaces of the polysilicon plugs 12 areexposed to an atmosphere in the capacitor hole 96. The side portions ofthe third inter-layer insulator 32 of silicon nitride and the topsurfaces of the polysilicon plugs 12 are then subjected to an oxidationprocess so that the side portions of silicon nitride are modified intosilicon oxynitride films (SiON films) 82, while the polysilicon plugs 12of polysilicon are modified into silicon oxide films 86. Namely, by theoxidation process, the silicon oxynitride films (SiON films) 82 areformed on the side edges of the third inter-layer insulator 32, whilethe silicon oxide films 86 are formed on the top surfaces of thepolysilicon plugs 12.

In some cases, the oxidation process may be realized by a thermaloxidation process that is carried out at 700° C. for 10 minutes, therebyforming the silicon oxynitride film 82 having a thickness ofapproximately 1 nanometer. The thermal oxidation process can be carriedout in either an oxygen atmosphere or a nitrogen atmosphere. When thethermal oxidation process is carried out in the oxygen atmosphere, theside portions of silicon nitride are oxidized by oxygen contained in theoxygen atmosphere. When the thermal oxidation process is carried out inthe nitrogen atmosphere, the side portions of silicon nitride areoxidized by oxygen and/or water that have been eliminated from thesecond and fourth inter-layer insulators 22 and 23 of silicon oxidewhich are exposed to the nitrogen atmosphere in the capacitor hole 96.

In other cases, the oxidation process may also be realized by a plasmaoxidation process, so that the side portions of silicon nitride areoxidized by oxygen that has been eliminated from the second and fourthinter-layer insulators 22 and 23 of silicon oxide which are exposed tothe plasma atmosphere in the capacitor hole 96.

A wet cleaning process is carried out to remove the silicon oxide films86 from the polysilicon plugs 12, while leaving the silicon oxynitridefilms (SiON films) 82 on the side edges of the third inter-layerinsulator 32. The wet cleaning process can be realized by using ahydrogen fluoride solution that is diluted with ammonium water, namelyBHF water, or a hydrogen fluoride solution that is diluted with water,namely DHF water. Use of BHF water or DHF water can remove the siliconoxide films 86 from the polysilicon plugs 12, while leaving the siliconoxynitride films (SiON films) 82 on the side edges of the thirdinter-layer insulator 32.

A chemical vapor deposition process is carried out to form adhesivelayers 81 and 81 a of titanium oxide (TiO). The titanium oxide adhesivelayer 81 is deposited on the surfaces of the second and fourthinter-layer insulators 22 and 23 of silicon oxide. The titanium oxideadhesive layer 81 a is deposited on the silicon oxynitride films (SiONfilms) 82 which is adjacent to the side edges of the third inter-layerinsulator 32. In some cases, the chemical vapor deposition process canbe carried out at 650° C. in a titanium tetrachloride (TiCl₄) gas. Thechemical vapor deposition process causes a reaction between titanium oftitanium tetrachloride (TiCl₄) and silicon oxide of the second andfourth inter-layer insulators 22 and 23, thereby forming the titaniumoxide adhesive layer 81 on the surfaces of the second and fourthinter-layer insulators 22 and 23. The chemical vapor deposition processalso causes another reaction between titanium of titanium tetrachloride(TiCl₄) and silicon oxynitride of the silicon oxynitride films (SiONfilms) 82, thereby forming the titanium oxide adhesive layer 81 a on thesilicon oxynitride films (SiON films) 82.

The top surfaces of the polysilicon plugs 12 are also exposed to thetitanium tetrachloride (TiCl₄) atmosphere in the capacitor hole 96 sincethe silicon oxide films 86 have been removed by the wet etching process.Thus, the chemical vapor deposition process also causes a silicidationreaction between titanium of titanium tetrachloride (TiCl₄) andpolysilicon of the polysilicon plugs 12, thereby forming titaniumsilicide films 50 on the top surfaces of the polysilicon plugs 12.Namely, the side and bottom walls of the capacitor hole 96 are coveredby the titanium oxide adhesive layers 81 and 81 a and the titaniumsilicide films 50.

The silicon oxynitride films (SiON films) 82 is adjacent to the sideedges of the third inter-layer insulator 32 of silicon nitride. Thetitanium oxide adhesive layer 81 a is also adjacent to the siliconoxynitride films (SiON films) 82. The silicon oxynitride films (SiONfilms) 82 is interposed as an intermediate layer between the thirdinter-layer insulator 32 of silicon nitride (SiN) and the titanium oxide(TiO) adhesive layer 81 a. Silicon oxynitride (SiON) has adhesiveness toboth titanium oxide (TiO) and silicon nitride (SiN). Thus, the siliconoxynitride films (SiON films) 82 have adhesiveness to the siliconnitride (SiN) third inter-layer insulator 32 and also to the titaniumoxide (TiO) adhesive layer 81 a. In other words, the silicon oxynitridefilms (SiON films) 82 provide enhanced adhesiveness between the siliconnitride (SiN) third inter-layer insulator 32 and the titanium oxide(TiO) adhesive layer 81 a.

A chemical vapor deposition process is carried out to form a titaniumnitride pedestal bottom electrode film 51 on the titanium oxide (TiO)adhesive layers 81 and 81 a and the titanium silicide films 50. Thetitanium nitride pedestal bottom electrode film 51 fills the capacitorhole 96 and also extends over the fourth inter-layer insulator 23.

The titanium nitride bottom electrode film 51 is adhered via thetitanium oxide (TiO) adhesive layer 81 to the silicon oxide fourthinter-layer insulator 23. Further, the titanium nitride bottom electrodefilm 51 is adhered via the titanium oxide (TiO) adhesive layer 81 a andthe silicon oxynitride films (SiON films) 82 to the silicon nitride(SiN) third inter-layer insulator 32. In other words, the titanium oxide(TiO) adhesive layer 81 provides adhesiveness between the titaniumnitride bottom electrode film 51 and the silicon oxide fourthinter-layer insulator 23. The titanium oxide (TiO) adhesive layer 81 aprovides adhesiveness between the titanium nitride bottom electrode film51 and the silicon oxynitride films (SiON films) 82. The siliconoxynitride films (SiON films) 82 also provide enhanced adhesivenessbetween the titanium oxide (TiO) adhesive layer 81 a and the siliconnitride (SiN) third inter-layer insulator 32. Thus, the titanium oxide(TiO) adhesive layer 81 a in combination with the silicon oxynitridefilms (SiON films) 82 provide enhanced adhesiveness between the titaniumnitride bottom electrode film 51 and the silicon nitride (SiN) thirdinter-layer insulator 32. The silicon oxynitride films (SiON films) 82may be regarded as an intermediate adhesive layer, or as an additionaladhesive layer in addition to the titanium oxide (TiO) adhesive layer 81a.

With reference to FIG. 27, the stack of the titanium nitride bottomelectrode film 51 and the titanium oxide (TiO) adhesive layer 81 has afirst portion which extends over the fourth inter-layer insulator 23 anda second portion which is present in the capacitor hole 96. A chemicalmechanical polishing process is carried out to remove the first portionof the stack of the titanium nitride pedestal bottom electrode film 51and the titanium oxide (TiO) adhesive layer 81. Namely, the chemicalmechanical polishing process is carried out to leave the second portionof the stack of the titanium nitride pedestal bottom electrode film 51and the titanium oxide (TiO) adhesive layers 81 and 81 a in thecapacitor hole 96. As a result of the chemical mechanical polishingprocess, the upper surface of the fourth inter-layer insulator 23 isshown, while the side and bottom walls of the capacitor hole 96 remainfilled by the remaining portion of the stack of the titanium nitridebottom electrode film 51 and the titanium oxide (TiO) adhesive layers 81and 81 a.

With reference to FIG. 28, the fourth inter-layer insulator 23 isselectively removed to form a capacitor hole which extends in the memorycell area 100. The titanium nitride pedestal bottom electrode film 51and the titanium oxide (TiO) adhesive layers 81 and 81 a remain in thememory cell area 100. The titanium nitride pedestal bottom electrodefilm 51 and the titanium oxide (TiO) adhesive layers 81 and 81 a arespatially separated from the side wall of the capacitor hole whichextends in the memory cell area 100. The fourth inter-layer insulator 23can be selectively removed by a photo lithography technique and a dryetching technique. In the dry etching process, the silicon nitride (SiN)third inter-layer insulator 32 performs as an etching stopper.

With reference to FIG. 29, a nitration process is carried out to nitratethe titanium oxide (TiO) adhesive layers 81 and 81 a, thereby forming atitanium nitride film 51 a. Namely, the titanium oxide (TiO) adhesivelayers 81 and 81 a are modified into the titanium nitride film 51 a, sothat the titanium nitride pedestal bottom electrode film 51 is coveredby the titanium nitride film 51 a. If the titanium oxide (TiO) adhesivelayers 81 and 81 a were present between the titanium nitride pedestalbottom electrode film 51 and the aluminum oxide capacitive insulatingfilm 52, then the charge storing capacity of the capacitor is reduced,and the leakage of current is increased. In the these points of view,the titanium oxide (TiO) adhesive layers 81 and 81 a are modified intothe titanium nitride film 51 a, so that there is no titanium oxide filmbetween the titanium nitride pedestal bottom electrode film 51 and thealuminum oxide capacitive insulating film 52. The nitration process canbe carried out by a plasma process using an ammonium (NH₃) atmosphere ora nitrogen atmosphere (N₂).

An aluminum oxide capacitive insulating film 52 is formed on thetitanium nitride film 51 a which covers the titanium nitride pedestalbottom electrode 51 as well as on the bottom and side walls of thecapacitor hole and over adjacent portions of the top surface of thefourth inter-layer insulator 23. Namely, the aluminum oxide capacitiveinsulating film 52 is formed on the titanium nitride film 51 a, thesilicon nitride third inter-layer insulator 32, the silicon oxynitridefilms 82, and the side wall and of the upper surface of the fourthinter-layer insulator 23. The aluminum oxide capacitive insulating film52 can be formed by using an atomic layer deposition process. Thethickness of the aluminum oxide capacitive insulating film 52 cantypically be, but is not limited to, 6 nanometers. A titanium nitridetop electrode 53 is formed on the aluminum oxide capacitive insulatingfilm 52. The titanium nitride top electrode 53 can be formed by using achemical vapor deposition process. The thickness of the titanium nitridetop electrode 53 can typically be, but is not limited to, 15 nanometers.The stack of the aluminum oxide capacitive insulating film 52 and thetitanium nitride top electrode 53 fills the cylinder-shaped gap and thecylinder-shaped center hollow.

The stack of the aluminum oxide capacitive insulating film 52 and thetitanium nitride top electrode 53 is selectively removed so as to leavethe stack in the capacitor hole 96 and over the adjacent portion of theupper surface of the fourth inter-layer insulator 23 of silicon oxide.

Over the memory cell area 100 and the peripheral circuit area 200, asilicon oxide fifth inter-layer insulator 24 is formed on the topelectrode 53 of the capacitor 54 and on the fourth inter-layer insulator24. In the same manners as described in the first embodiment, first,second, and third metal plugs 42, 43, and 44 are formed. The first andsecond contact plugs 42 and 43 contact with the metal plug 41 and thefirst-level interconnection 8 a. The first contact plug 43 iselectrically connected through the metal plug 41 to the diffusion layer7 of the peripheral circuit transistor. The second contact plug 44 iselectrically connected through the first-level interconnection 8 a andthe metal plug 41 a to the diffusion layer 7 a of the peripheral circuittransistor. The third contact plug 44 contacts with the top electrode 53of the capacitor 54. Second-level interconnections 61 and 61 a are alsoformed. The second-level interconnection 61 contacts with the second andthird contact plugs 43 and 44. Namely, the second-level interconnection61 electrically connects between the first and third contact plugs 43and 44. The additional second-level interconnection 61 a contacts withthe first contact plug 42. As a result, the semiconductor memory deviceof FIG. 23 is completed.

In accordance with the third embodiment, the invention is applied to thecapacitor with the pedestal bottom electrode. The above-describedprocess can prevent the pedestal bottom electrode from falling downduring the process for selectively removing the fourth inter-layerinsulator 23 in the memory cell area 100.

It is also possible as a modification that the capacitor 54 may be acrown capacitor with a crown bottom electrode which has a cylindershape, wherein the crown bottom electrode have inner and outer sidewalls, both of which are adjacent to the capacitive insulating film 52.The above-described process can prevent the crown bottom electrode fromfalling down during the process for selectively removing the fourthinter-layer insulator 23 in the memory cell area 100.

As described above, after the pedestal bottom electrode 51 is formed inthe capacitor hole 96, the fourth inter-layer insulato4r 23 isselectively removed in the memory cell area 100. The fourth inter-layerinsulato4r 23 can be selectively removed by the photo-lithographytechnique and the dry etching process. It is also possible as amodification to use a wet etching process, instead of the dry etchingprocess, for selectively removing the fourth inter-layer insulator 23 inthe memory cell area 100. The wet etching process can be carried outusing the third inter-layer insulator 32 as an etching stopper. Asdescribed above, silicon oxynitride films 82 are interposed between thepedestal bottom electrode film 51 and the silicon nitride thirdinter-layer insulator 32. The silicon oxynitride films 82 provideenhanced adhesiveness between the pedestal bottom electrode film 51 andthe silicon nitride third inter-layer insulator 32. The siliconoxynitride films 82 can prevent the pedestal bottom electrode film 51from falling down during the wet etching process using an etchant.Namely, the silicon oxynitride films 82 can prevent the etchant frompenetrating between the titanium nitride pedestal bottom electrode 51and the third inter-layer insulator 32.

As described above, the titanium oxide (TiO) adhesive layers 81 a incombination with silicon oxynitride films 82 are interposed between thepedestal bottom electrode film 51 and the silicon nitride thirdinter-layer insulator 32. The titanium oxide (TiO) adhesive layers 81 ain combination with the silicon oxynitride films 82 provide enhancedadhesiveness between the pedestal bottom electrode film 51 and thesilicon nitride third inter-layer insulator 32.

In accordance with the third embodiment, the third inter-layer insulator32 is made of silicon nitride. It is also possible as a modificationthat the third inter-layer insulator 32 is made of silicon oxynitride asdescribed in the second embodiment. In this modified case, the titaniumoxide (TiO) adhesive layers 81 a are interposed between the pedestalbottom electrode film 51 and the silicon oxynitride third inter-layerinsulator 32. The titanium oxide (TiO) adhesive layers 81 a provideenhanced adhesiveness between the pedestal bottom electrode film 51 andthe silicon oxynitride third inter-layer insulator 32.

Typical examples of the semiconductor memory device described above mayinclude, but are not limited to, DRAM and hybrid LSI with DRAM.

While preferred embodiments of the invention have been described andillustrated above, it should be understood that these are exemplary ofthe invention and are not to be considered as limiting. Additions,omissions, substitutions, and other modifications can be made withoutdeparting from the spirit or scope of the present invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description, and is only limited by the scope of theappended claims.

1. A semiconductor device comprising: a first insulating layer thatincludes a first insulating film, the first insulating layered structurehaving a first hole; a capacitor in the first hole, the capacitorcomprising bottom and top electrodes and a capacitive insulating filmthat is sandwiched between the bottom and top electrodes; an adhesivelayer that contacts with the bottom electrode, the adhesive layer havingadhesiveness to the bottom electrode; and an intermediate layer that isinterposed between the adhesive layer and the first insulating film, theintermediate layer contacting with the adhesive layer and with the firstinsulating film, the intermediate layer having adhesiveness to theadhesive layer and to the first insulating film.
 2. The semiconductordevice according to claim 1, wherein the bottom electrode comprisesnitride containing a first metal, the adhesive layer comprises one ofthe first metal and oxide containing the first metal, the intermediatelayer comprises oxynitride containing a first semiconductor, and thefirst insulating film comprises nitride containing the firstsemiconductor.
 3. The semiconductor device according to claim 2, whereinthe bottom electrode covers bottom and side walls of the first hole. 4.The semiconductor device according to claim 2, wherein the intermediatelayer is a modified portion of the first insulating film, the modifiedportion is adjacent to the adhesive layer.
 5. The semiconductor deviceaccording to claim 4, wherein the first semiconductor is silicon, thefirst insulating film comprises silicon nitride, and the modifiedportion of the first insulating film comprises silicon oxynitride. 6.The semiconductor device according to claim 5, wherein the firstinsulating layer comprises a stack of a silicon oxide film and the firstinsulating film, and the silicon oxide film extends over the firstinsulating film, and the first hole penetrates the stack.
 7. Thesemiconductor device according to claim 5, wherein the first metal istitanium, the adhesive layer comprises one of titanium and titaniumoxide, and the bottom electrode comprises titanium nitride.
 8. Thesemiconductor device according to claim 7, further comprising: at leastone polysilicon plug; at least one titanium silicide layer between theat least one polysilicon plug and the bottom electrode, the titaniumsilicide layer contacting with the at least one polysilicon plug andwith the bottom electrode; and at least one memory cell switchingtransistor electrically connected through the at least one polysiliconplug and the titanium silicide layer to the bottom electrode.
 9. Thesemiconductor device according to claim 7, wherein the bottom electrodehas one of a cylinder shape and a modified cylinder shape, and themodified cylinder shape is a three-dimensional shape that has coaxialinside and outside cylinder walls and a torus bottom wall thatcommunicates between the coaxial inside and outside cylinder walls, andthe stack of the capacitive insulating film and the top electrode coversat least one of opposing surfaces of the bottom electrode.
 10. Thesemiconductor device according to claim 1, wherein the bottom electrodehas a pedestal shape and fills the first hole, and the stack of thecapacitive insulating film and the top electrode covers an outsidesurface of the bottom electrode.
 11. A semiconductor device comprising:a first insulating layer that includes a first insulating film, thefirst insulating layered structure having a first hole; a capacitor inthe first hole, the capacitor comprising bottom and top electrodes and acapacitive insulating film that is sandwiched between the bottom and topelectrodes; and an adhesive layer that is interposed between the bottomelectrode and the first insulating film, the adhesive layer contactingwith the bottom electrode and with the first insulating film, theadhesive layer having adhesiveness to the bottom electrode and to thefirst insulating film.
 12. The semiconductor device according to claim11, wherein the bottom electrode comprises nitride containing a firstmetal, the adhesive layer comprises one of the first metal and oxidecontaining the first metal, and the first insulating film comprisesoxynitride containing a first semiconductor.
 13. The semiconductordevice according to claim 2, wherein the bottom electrode covers bottomand side walls of the first hole.
 14. The semiconductor device accordingto claim 12, wherein the first semiconductor is silicon, the firstinsulating film comprises silicon oxynitride.
 15. The semiconductordevice according to claim 14, wherein the first insulating layercomprises a stack of a silicon oxide film and the first insulating film,and the silicon oxide film extends over the first insulating film. 16.The semiconductor device according to claim 14, wherein the first metalis titanium, the adhesive layer comprises one of titanium and titaniumoxide, and the bottom electrode comprises titanium nitride.
 17. Thesemiconductor device according to claim 16, further comprising: at leastone polysilicon plug; at least one titanium silicide layer between theat least one polysilicon plug and the bottom electrode, the titaniumsilicide layer contacting with the at least one polysilicon plug andwith the bottom electrode; and at least one memory cell switchingtransistor electrically connected through the at least one polysiliconplug and the titanium silicide layer to the bottom electrode.
 18. Thesemiconductor device according to claim 16, wherein the bottom electrodehas one of a cylinder shape and a modified cylinder shape, and themodified cylinder shape is a three-dimensional shape that has coaxialinside and outside cylinder walls and a torus bottom wall thatcommunicates between the coaxial inside and outside cylinder walls, andthe stack of the capacitive insulating film and the top electrode coversat least one of opposing surfaces of the bottom electrode.
 19. Thesemiconductor device according to claim 11, wherein the bottom electrodehas a pedestal shape and fills the first hole, and the stack of thecapacitive insulating film and the top electrode covers an outsidesurface of the bottom electrode.
 20. A method of forming a semiconductordevice with a capacitor, the method comprising: forming a first hole ina first insulating layer that includes a first insulating film, thefirst insulating film having a first portion that is exposed to thefirst hole; modifying the first portion to form an intermediate layerthat adjacent to the first insulating film, the intermediate layer beingexposed to the first hole, the intermediate layer having adhesiveness tothe first insulating film; forming an adhesive layer that contacts withthe intermediate layer and with bottom and side walls of the first hole,the adhesive layer having adhesiveness to the intermediate layer;forming a bottom electrode that contacts with the adhesive layer, theadhesive layer having adhesiveness to the bottom electrode; forming acapacitive insulating film that contacts with the bottom electrode; andforming a top electrode that contacts with the contacts with thecapacitive insulating film.
 21. The method according to claim 20,wherein the bottom electrode comprises nitride containing a first metal,the adhesive layer comprises one of the first metal and oxide containingthe first metal, the intermediate layer comprises oxynitride containinga first semiconductor, and the first insulating film comprises nitridecontaining the first semiconductor.
 22. The method according to claim21, wherein the first semiconductor is silicon, the first insulatingfilm comprises silicon nitride, and modifying the first portioncomprises modifying silicon nitride of the first portion into siliconoxynitride.
 23. The method according to claim 22, wherein forming thefirst hole comprises forming the first hole that penetrate a stack of asilicon oxide film and the first insulating film of silicon nitride, thesilicon oxide film extends over the first insulating film.
 24. Themethod according to claim 23, wherein forming the first hole comprises:carrying out a first etching process for selectively etching the siliconoxide film under a first condition that a first etching rate of thefirst insulating film of silicon nitride is higher than a second etchingrate of the silicon oxide film; and carrying out a second etchingprocess for selectively etching the first insulating film of siliconnitride under a second condition that a third etching rate of thesilicon oxide film is higher than a fourth etching rate of the firstinsulating film of silicon nitride.
 25. The method according to claim22, further comprising: forming at least one polysilicon plug in asecond insulating layer that underlies the first insulating layer, andwherein forming the first hole comprises forming the first hole so thata second portion of the at least one polysilicon plug is exposed to thefirst hole, and modifying the first portion comprises modifying thefirst and second portion to respectively form the intermediate layer anda silicon oxide portion of the at least one polysilicon plug, thesilicon oxide portion being adjacent to the first hole and also adjacentto the at least one polysilicon plug, and the method further comprises:removing the silicon oxide portion before forming an adhesive layer. 26.The method according to claim 25, wherein forming the adhesive layercomprises carrying out a chemical vapor deposition using a titaniumtetrachloride gas to form the adhesive layer and a titanium silicidelayer on the at least one polysilicon plug.
 27. The method according toclaim 26, further comprising: removing a peripheral portion of the firstinsulating layer after forming the bottom electrode, thereby forming agap between the first insulating layer and the adhesive layer thatcovers a surface of the bottom electrode, the peripheral portionsurrounding the adhesive layer and the bottom electrode, the peripheralportion being adjacent to the adhesive layer and the bottom electrode;and carrying out a nitration process for nitrating the adhesive layer toform a titanium nitride film that covers the surface of the bottomelectrode.
 28. The method according to claim 27, wherein removing theperipheral portion is carried out using the first insulating film ofsilicon nitride as an etching stopper.
 29. A method of forming asemiconductor device with a capacitor, the method comprising: forming afirst hole in a first insulating layer that includes a first insulatingfilm, the first insulating film having a first portion that is exposedto the first hole; forming an adhesive layer that contacts with thefirst portion and with bottom and side walls of the first hole, theadhesive layer having adhesiveness to the first portion; forming abottom electrode that contacts with the adhesive layer, the adhesivelayer having adhesiveness to the bottom electrode; forming a capacitiveinsulating film that contacts with the bottom electrode; and forming atop electrode that contacts with the contacts with the capacitiveinsulating film.
 30. The method according to claim 29, wherein thebottom electrode comprises nitride containing a first metal, theadhesive layer comprises one of the first metal and oxide containing thefirst metal, and the first insulating film comprises oxynitridecontaining a first semiconductor.
 31. The method according to claim 30,further comprising: forming at least one polysilicon plug in a secondinsulating layer that underlies the first insulating layer, and whereinforming the first hole comprises forming the first hole so that a secondportion of the at least one polysilicon plug is exposed to the firsthole, and forming the adhesive layer comprises carrying out a chemicalvapor deposition using a titanium tetrachloride gas to form the adhesivelayer and a titanium silicide layer on the at least one polysiliconplug.
 32. The method according to claim 31, further comprising: removinga peripheral portion of the first insulating layer after forming thebottom electrode, thereby forming a gap between the first insulatinglayer and the adhesive layer that covers a surface of the bottomelectrode, the peripheral portion surrounding and being adjacent to theadhesive layer and the bottom electrode; and carrying out a nitrationprocess for nitrating the adhesive layer to form a titanium nitride filmthat covers the surface of the bottom electrode.
 33. The methodaccording to claim 32, wherein removing the peripheral portion iscarried out using the first insulating film of silicon nitride as anetching stopper.